upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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347 lines
11 KiB
347 lines
11 KiB
22 years ago
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/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002
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* Gregory E. Allen, gallen@arlut.utexas.edu
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* Matthew E. Karger, karger@arlut.utexas.edu
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* Applied Research Laboratories, The University of Texas at Austin
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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*
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* Configuration settings for the utx8245 board.
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*
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*/
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/* ------------------------------------------------------------------------- */
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC824X 1
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#define CONFIG_MPC8245 1
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#define CONFIG_UTX8245 1
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#define DEBUG 1
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 57600
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
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#define CONFIG_BOOTCOMMAND "bootm FF920000 FF800000" /* autoboot command */
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#define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */
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#define CONFIG_ETHADDR 41:52:4c:61:00:01 /* MAC address */
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#define CONFIG_SERVERIP 10.8.17.105
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_BDI | CFG_CMD_PCI \
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| CFG_CMD_FLASH | CFG_CMD_MEMORY \
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| CFG_CMD_ENV | CFG_CMD_CONSOLE \
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| CFG_CMD_LOADS | CFG_CMD_LOADB \
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| CFG_CMD_IMI | CFG_CMD_CACHE \
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| CFG_CMD_RUN | CFG_CMD_ECHO \
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| CFG_CMD_REGINFO | CFG_CMD_NET\
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| CFG_CMD_DHCP)
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/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
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*/
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
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/*-----------------------------------------------------------------------
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* PCI configuration
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_PCI /* include pci support */
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#undef CONFIG_PCI_PNP
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_NET_MULTI
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#define CONFIG_EEPRO100
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#define PCI_ENET0_IOADDR 0x80000000
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#define PCI_ENET0_MEMADDR 0x80000000
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#define PCI_FIREWIRE_IOADDR 0x81000000
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#define PCI_FIREWIRE_MEMADDR 0x81000000
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_MAX_RAM_SIZE 0x10000000 /* amount of SDRAM */
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/* even though FLASHP_BASE is FF800000, with 2MB on RCS0, the
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* reset vector is actually located at FF800100, but the 8245
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* takes care of us.
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*/
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#define CFG_RESET_ADDRESS 0xFFF00100
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#define CFG_EUMB_ADDR 0xFC000000
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*#define CFG_DRAM_TEST 1 */
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#define CFG_MEMTEST_START 0x00003000 /* memtest works on 0...256 MB */
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#define CFG_MEMTEST_END 0x0ff8ffa8 /* in SDRAM, skips exception */
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/* vectors and U-Boot */
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/*--------------------------------------------------------------------
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* Definitions for initial stack pointer and data area
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*------------------------------------------------------------------*/
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#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for */
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/* initial data */
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#define CFG_INIT_RAM_ADDR 0x40000000
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#define CFG_INIT_RAM_END 0x1000
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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/*--------------------------------------------------------------------
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* NS16550 Configuration
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*------------------------------------------------------------------*/
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 1
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#define CFG_NS16550_CLK get_bus_freq(0)
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#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
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#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
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/*--------------------------------------------------------------------
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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* For the detail description refer to the MPC8240 user's manual.
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*------------------------------------------------------------------*/
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#define CONFIG_SYS_CLK_FREQ 33000000
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#define CFG_HZ 1000
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#define CFG_ETH_DEV_FN 0x7800
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#define CFG_ETH_IOBASE 0x00104000
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/*--------------------------------------------------------------------
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* Memory Control Configuration Register values
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* - see sec. 4.12 of MPC8245 UM
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*------------------------------------------------------------------*/
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/* MCCR1 */
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#define CFG_ROMNAL 0
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#define CFG_ROMFAL 2 /* (tacc=70ns)*mem_freq - 2 */
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#define CFG_BANK0_ROW 2 /* SDRAM bank 7-0 row address */
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#define CFG_BANK1_ROW 2 /* bit count */
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#define CFG_BANK2_ROW 0
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#define CFG_BANK3_ROW 0
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#define CFG_BANK4_ROW 0
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#define CFG_BANK5_ROW 0
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#define CFG_BANK6_ROW 0
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#define CFG_BANK7_ROW 0
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/* MCCR2, refresh interval clock cycles */
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#define CFG_REFINT 480 /* 33 MHz SDRAM clock was 480 */
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/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4 */
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#define CFG_BSTOPRE 1023 /* burst to precharge[0..9], */
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/* sets open page interval */
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/* MCCR3 */
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#define CFG_REFREC 5 /* Refresh to activate interval, trc */
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/* MCCR4 */
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#define CFG_PRETOACT 2 /* trp */
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#define CFG_ACTTOPRE 7 /* trcd + (burst length - 1) + tdrl */
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#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
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#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */
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#define CFG_ACTORW 2 /* trcd min */
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#define CFG_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
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#define CFG_REGISTERD_TYPE_BUFFER 1
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#define CFG_EXTROM 1
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#define CFG_REGDIMM 0
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/* calculate according to formula in sec. 6-22 of 8245 UM */
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#define CFG_PGMAX 50 /* how long the 8245 retains the */
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/* currently accessed page in memory */
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/* was 45 */
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#define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note */
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/* bottom 3 bits MUST be 0 */
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#define CFG_DLL_MAX_DELAY 0x04
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#define CFG_DLL_EXTEND 0x80
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#define CFG_PCI_HOLD_DEL 0x20
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/* Memory bank settings.
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* Only bits 20-29 are actually used from these values to set the
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* start/end addresses. The upper two bits will always be 0, and the lower
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* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
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* address. Refer to the MPC8245 user manual.
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*/
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#define CFG_BANK0_START 0x00000000
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#define CFG_BANK0_END (CFG_MAX_RAM_SIZE/2 - 1)
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#define CFG_BANK0_ENABLE 1
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#define CFG_BANK1_START CFG_MAX_RAM_SIZE/2
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#define CFG_BANK1_END (CFG_MAX_RAM_SIZE - 1)
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#define CFG_BANK1_ENABLE 1
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#define CFG_BANK2_START 0x3ff00000 /* not available in this design */
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#define CFG_BANK2_END 0x3fffffff
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#define CFG_BANK2_ENABLE 0
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#define CFG_BANK3_START 0x3ff00000
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#define CFG_BANK3_END 0x3fffffff
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#define CFG_BANK3_ENABLE 0
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#define CFG_BANK4_START 0x3ff00000
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#define CFG_BANK4_END 0x3fffffff
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#define CFG_BANK4_ENABLE 0
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#define CFG_BANK5_START 0x3ff00000
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#define CFG_BANK5_END 0x3fffffff
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#define CFG_BANK5_ENABLE 0
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#define CFG_BANK6_START 0x3ff00000
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#define CFG_BANK6_END 0x3fffffff
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#define CFG_BANK6_ENABLE 0
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#define CFG_BANK7_START 0x3ff00000
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#define CFG_BANK7_END 0x3fffffff
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#define CFG_BANK7_ENABLE 0
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/*--------------------------------------------------------------------
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* 4.4 - Output Driver Control Register
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*------------------------------------------------------------------*/
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#define CFG_ODCR 0xe5
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/*--------------------------------------------------------------------
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* 4.8 - Error Handling Registers
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*------------------------------------------------------------------*/
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#define CFG_ERRENR1 0x11 /* enable SDRAM refresh overflow error */
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/* SDRAM 0-256 MB */
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#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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/* stack in dcache */
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#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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/* PCI memory */
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#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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/* Flash, config addrs, etc. */
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#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CFG_DBAT0L CFG_IBAT0L
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#define CFG_DBAT0U CFG_IBAT0U
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#define CFG_DBAT1L CFG_IBAT1L
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#define CFG_DBAT1U CFG_IBAT1U
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#define CFG_DBAT2L CFG_IBAT2L
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#define CFG_DBAT2U CFG_IBAT2U
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#define CFG_DBAT3L CFG_IBAT3L
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#define CFG_DBAT3U CFG_IBAT3U
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization (AMD AM29LV116D)
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*/
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#define CFG_FLASH_BASE 0xFF800000
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#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
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#define CFG_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/* Warning: environment is not EMBEDDED in the U-Boot code.
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* It's stored in flash separately.
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*/
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR 0xFF9FA000 /* flash sector SA33 */
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#define CFG_ENV_SIZE 0x2000 /* Size of the Environment */
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#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
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#define CFG_ENV_SECT_SIZE 0x2000 /* Size of the Environment Sector */
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#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
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#undef CFG_RAMBOOT
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#else
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#define CFG_RAMBOOT
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 32
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Internal Definitions
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||
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#endif /* __CONFIG_H */
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