upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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41 lines
1.5 KiB
41 lines
1.5 KiB
13 years ago
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/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __AVR32_CACHE_H__
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#define __AVR32_CACHE_H__
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/*
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* Since the AVR32 architecture has a queryable cacheline size with a maximum
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* value of 256 we set the DMA buffer alignemnt requirement to this maximum
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* value. The board config can override this if it knows that the cacheline
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* size is a smaller value. AVR32 boards use the CONFIG_SYS_DCACHE_LINESZ
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* macro to specify cache line size, so if it is set we use it instead.
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*/
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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#elif defined(CONFIG_SYS_DCACHE_LINESZ)
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#define ARCH_DMA_MINALIGN CONFIG_SYS_DCACHE_LINESZ
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#else
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#define ARCH_DMA_MINALIGN 256
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#endif
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#endif /* __AVR32_CACHE_H__ */
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