upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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41 lines
838 B
41 lines
838 B
9 years ago
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/*
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* Copyright (c) 2015 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <cros_ec.h>
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#include <errno.h>
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#include <i2c.h>
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static int cros_ec_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
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{
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return 0;
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}
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static int cros_ec_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
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int nmsgs)
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{
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return cros_ec_i2c_tunnel(dev->parent, msg, nmsgs);
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}
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static const struct dm_i2c_ops cros_ec_i2c_ops = {
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.xfer = cros_ec_i2c_xfer,
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.set_bus_speed = cros_ec_i2c_set_bus_speed,
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};
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static const struct udevice_id cros_ec_i2c_ids[] = {
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{ .compatible = "google,cros-ec-i2c-tunnel" },
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{ }
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};
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U_BOOT_DRIVER(cros_ec_tunnel) = {
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.name = "cros_ec_tunnel",
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.id = UCLASS_I2C,
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.of_match = cros_ec_i2c_ids,
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.ops = &cros_ec_i2c_ops,
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};
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