upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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117 lines
3.5 KiB
117 lines
3.5 KiB
17 years ago
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/* SPARC Processor specifics
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* taken from the SPARC port of Linux (ptrace.h).
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*
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* (C) Copyright 2007
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* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef __ASM_SPARC_PROCESSOR_H
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#define __ASM_SPARC_PROCESSOR_H
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#include <asm/arch/asi.h>
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17 years ago
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#ifdef CONFIG_LEON
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/* All LEON processors supported */
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#include <asm/leon.h>
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#else
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/* other processors */
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17 years ago
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#error Unknown SPARC Processor
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17 years ago
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#endif
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17 years ago
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#ifndef __ASSEMBLY__
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/* flush data cache */
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static __inline__ void sparc_dcache_flush_all(void)
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{
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__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_DFLUSH):"memory");
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}
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/* flush instruction cache */
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static __inline__ void sparc_icache_flush_all(void)
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{
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__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_IFLUSH):"memory");
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}
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/* do a cache miss load */
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static __inline__ unsigned long long sparc_load_reg_cachemiss_qword(unsigned
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long paddr)
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{
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unsigned long long retval;
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__asm__ __volatile__("ldda [%1] %2, %0\n\t":
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"=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
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return retval;
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}
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static __inline__ unsigned long sparc_load_reg_cachemiss(unsigned long paddr)
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{
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unsigned long retval;
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__asm__ __volatile__("lda [%1] %2, %0\n\t":
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"=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
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return retval;
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}
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static __inline__ unsigned short sparc_load_reg_cachemiss_word(unsigned long
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paddr)
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{
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unsigned short retval;
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__asm__ __volatile__("lduha [%1] %2, %0\n\t":
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"=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
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return retval;
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}
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static __inline__ unsigned char sparc_load_reg_cachemiss_byte(unsigned long
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paddr)
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{
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unsigned char retval;
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__asm__ __volatile__("lduba [%1] %2, %0\n\t":
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"=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
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return retval;
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}
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/* do a physical address bypass write, i.e. for 0x80000000 */
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static __inline__ void sparc_store_reg_bypass(unsigned long paddr,
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unsigned long value)
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{
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__asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(value), "r"(paddr),
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"i"(ASI_BYPASS):"memory");
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}
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static __inline__ unsigned long sparc_load_reg_bypass(unsigned long paddr)
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{
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unsigned long retval;
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__asm__ __volatile__("lda [%1] %2, %0\n\t":
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"=r"(retval):"r"(paddr), "i"(ASI_BYPASS));
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return retval;
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}
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/* Macros for bypassing cache when reading */
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#define SPARC_NOCACHE_READ_DWORD(address) sparc_load_reg_cachemiss_qword((unsigned int)(address))
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#define SPARC_NOCACHE_READ(address) sparc_load_reg_cachemiss((unsigned int)(address))
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#define SPARC_NOCACHE_READ_HWORD(address) sparc_load_reg_cachemiss_word((unsigned int)(address))
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#define SPARC_NOCACHE_READ_BYTE(address) sparc_load_reg_cachemiss_byte((unsigned int)(address))
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#define SPARC_BYPASS_READ(address) sparc_load_reg_bypass((unsigned int)(address))
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#define SPARC_BYPASS_WRITE(address,value) sparc_store_reg_bypass((unsigned int)(address),(unsigned int)(value))
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#endif
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#endif /* __ASM_SPARC_PROCESSOR_H */
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