upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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307 lines
12 KiB
307 lines
12 KiB
20 years ago
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __address_h
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#define __address_h 1
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#define KS8695_SDRAM_START 0x00000000
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#define KS8695_SDRAM_SIZE 0x01000000
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#define KS8695_MEM_SIZE KS8695_SDRAM_SIZE
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#define KS8695_MEM_START KS8695_SDRAM_START
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#define KS8695_PCMCIA_IO_BASE 0x03800000
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#define KS8695_PCMCIA_IO_SIZE 0x00040000
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#define KS8695_IO_BASE 0x03FF0000
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#define KS8695_IO_SIZE 0x00010000
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#define KS8695_SYSTEN_CONFIG 0x00
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#define KS8695_SYSTEN_BUS_CLOCK 0x04
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#define KS8695_FLASH_START 0x02800000
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#define KS8695_FLASH_SIZE 0x00400000
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/*i/o control registers offset difinitions*/
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#define KS8695_IO_CTRL0 0x4000
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#define KS8695_IO_CTRL1 0x4004
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#define KS8695_IO_CTRL2 0x4008
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#define KS8695_IO_CTRL3 0x400C
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/*memory control registers offset difinitions*/
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#define KS8695_MEM_CTRL0 0x4010
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#define KS8695_MEM_CTRL1 0x4014
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#define KS8695_MEM_CTRL2 0x4018
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#define KS8695_MEM_CTRL3 0x401C
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#define KS8695_MEM_GENERAL 0x4020
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#define KS8695_SDRAM_CTRL0 0x4030
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#define KS8695_SDRAM_CTRL1 0x4034
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#define KS8695_SDRAM_GENERAL 0x4038
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#define KS8695_SDRAM_BUFFER 0x403C
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#define KS8695_SDRAM_REFRESH 0x4040
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/*WAN control registers offset difinitions*/
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#define KS8695_WAN_DMA_TX 0x6000
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#define KS8695_WAN_DMA_RX 0x6004
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#define KS8695_WAN_DMA_TX_START 0x6008
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#define KS8695_WAN_DMA_RX_START 0x600C
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#define KS8695_WAN_TX_LIST 0x6010
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#define KS8695_WAN_RX_LIST 0x6014
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#define KS8695_WAN_MAC_LOW 0x6018
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#define KS8695_WAN_MAC_HIGH 0x601C
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#define KS8695_WAN_MAC_ELOW 0x6080
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#define KS8695_WAN_MAC_EHIGH 0x6084
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/*LAN control registers offset difinitions*/
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#define KS8695_LAN_DMA_TX 0x8000
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#define KS8695_LAN_DMA_RX 0x8004
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#define KS8695_LAN_DMA_TX_START 0x8008
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#define KS8695_LAN_DMA_RX_START 0x800C
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#define KS8695_LAN_TX_LIST 0x8010
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#define KS8695_LAN_RX_LIST 0x8014
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#define KS8695_LAN_MAC_LOW 0x8018
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#define KS8695_LAN_MAC_HIGH 0x801C
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#define KS8695_LAN_MAC_ELOW 0X8080
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#define KS8695_LAN_MAC_EHIGH 0X8084
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/*HPNA control registers offset difinitions*/
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#define KS8695_HPNA_DMA_TX 0xA000
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#define KS8695_HPNA_DMA_RX 0xA004
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#define KS8695_HPNA_DMA_TX_START 0xA008
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#define KS8695_HPNA_DMA_RX_START 0xA00C
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#define KS8695_HPNA_TX_LIST 0xA010
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#define KS8695_HPNA_RX_LIST 0xA014
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#define KS8695_HPNA_MAC_LOW 0xA018
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#define KS8695_HPNA_MAC_HIGH 0xA01C
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#define KS8695_HPNA_MAC_ELOW 0xA080
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#define KS8695_HPNA_MAC_EHIGH 0xA084
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/*UART control registers offset difinitions*/
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#define KS8695_UART_RX_BUFFER 0xE000
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#define KS8695_UART_TX_HOLDING 0xE004
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#define KS8695_UART_FIFO_CTRL 0xE008
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#define KS8695_UART_FIFO_TRIG01 0x00
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#define KS8695_UART_FIFO_TRIG04 0x80
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#define KS8695_UART_FIFO_TXRST 0x03
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#define KS8695_UART_FIFO_RXRST 0x02
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#define KS8695_UART_FIFO_FEN 0x01
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#define KS8695_UART_LINE_CTRL 0xE00C
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#define KS8695_UART_LINEC_BRK 0x40
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#define KS8695_UART_LINEC_EPS 0x10
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#define KS8695_UART_LINEC_PEN 0x08
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#define KS8695_UART_LINEC_STP2 0x04
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#define KS8695_UART_LINEC_WLEN8 0x03
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#define KS8695_UART_LINEC_WLEN7 0x02
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#define KS8695_UART_LINEC_WLEN6 0x01
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#define KS8695_UART_LINEC_WLEN5 0x00
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#define KS8695_UART_MODEM_CTRL 0xE010
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#define KS8695_UART_MODEMC_RTS 0x02
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#define KS8695_UART_MODEMC_DTR 0x01
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#define KS8695_UART_LINE_STATUS 0xE014
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#define KS8695_UART_LINES_TXFE 0x20
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#define KS8695_UART_LINES_BE 0x10
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#define KS8695_UART_LINES_FE 0x08
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#define KS8695_UART_LINES_PE 0x04
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#define KS8695_UART_LINES_OE 0x02
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#define KS8695_UART_LINES_RXFE 0x01
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#define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE)
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#define KS8695_UART_MODEM_STATUS 0xE018
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#define KS8695_UART_MODEM_DCD 0x80
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#define KS8695_UART_MODEM_DSR 0x20
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#define KS8695_UART_MODEM_CTS 0x10
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#define KS8695_UART_MODEM_DDCD 0x08
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#define KS8695_UART_MODEM_DDSR 0x02
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#define KS8695_UART_MODEM_DCTS 0x01
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#define UART8695_MODEM_ANY 0xFF
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#define KS8695_UART_DIVISOR 0xE01C
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#define KS8695_UART_STATUS 0xE020
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/*Interrupt controlller registers offset difinitions*/
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#define KS8695_INT_CONTL 0xE200
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#define KS8695_INT_ENABLE 0xE204
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#define KS8695_INT_ENABLE_MODEM 0x0800
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#define KS8695_INT_ENABLE_ERR 0x0400
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#define KS8695_INT_ENABLE_RX 0x0200
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#define KS8695_INT_ENABLE_TX 0x0100
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#define KS8695_INT_STATUS 0xE208
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#define KS8695_INT_WAN_PRIORITY 0xE20C
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#define KS8695_INT_HPNA_PRIORITY 0xE210
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#define KS8695_INT_LAN_PRIORITY 0xE214
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#define KS8695_INT_TIMER_PRIORITY 0xE218
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#define KS8695_INT_UART_PRIORITY 0xE21C
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#define KS8695_INT_EXT_PRIORITY 0xE220
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#define KS8695_INT_CHAN_PRIORITY 0xE224
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#define KS8695_INT_BUSERROR_PRO 0xE228
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#define KS8695_INT_MASK_STATUS 0xE22C
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#define KS8695_FIQ_PEND_PRIORITY 0xE230
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#define KS8695_IRQ_PEND_PRIORITY 0xE234
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/*timer registers offset difinitions*/
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#define KS8695_TIMER_CTRL 0xE400
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#define KS8695_TIMER1 0xE404
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#define KS8695_TIMER0 0xE408
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#define KS8695_TIMER1_PCOUNT 0xE40C
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#define KS8695_TIMER0_PCOUNT 0xE410
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/*GPIO registers offset difinitions*/
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#define KS8695_GPIO_MODE 0xE600
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#define KS8695_GPIO_CTRL 0xE604
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#define KS8695_GPIO_DATA 0xE608
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/*SWITCH registers offset difinitions*/
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#define KS8695_SWITCH_CTRL0 0xE800
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#define KS8695_SWITCH_CTRL1 0xE804
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#define KS8695_SWITCH_PORT1 0xE808
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#define KS8695_SWITCH_PORT2 0xE80C
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#define KS8695_SWITCH_PORT3 0xE810
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#define KS8695_SWITCH_PORT4 0xE814
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#define KS8695_SWITCH_PORT5 0xE818
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#define KS8695_SWITCH_AUTO0 0xE81C
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#define KS8695_SWITCH_AUTO1 0xE820
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#define KS8695_SWITCH_LUE_CTRL 0xE824
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#define KS8695_SWITCH_LUE_HIGH 0xE828
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#define KS8695_SWITCH_LUE_LOW 0xE82C
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#define KS8695_SWITCH_ADVANCED 0xE830
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#define KS8695_SWITCH_LPPM12 0xE874
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#define KS8695_SWITCH_LPPM34 0xE878
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/*host communication registers difinitions*/
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#define KS8695_DSCP_HIGH 0xE834
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#define KS8695_DSCP_LOW 0xE838
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#define KS8695_SWITCH_MAC_HIGH 0xE83C
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#define KS8695_SWITCH_MAC_LOW 0xE840
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/*miscellaneours registers difinitions*/
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#define KS8695_MANAGE_COUNTER 0xE844
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#define KS8695_MANAGE_DATA 0xE848
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#define KS8695_LAN12_POWERMAGR 0xE84C
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#define KS8695_LAN34_POWERMAGR 0xE850
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#define KS8695_DEVICE_ID 0xEA00
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#define KS8695_REVISION_ID 0xEA04
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#define KS8695_MISC_CONTROL 0xEA08
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#define KS8695_WAN_CONTROL 0xEA0C
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#define KS8695_WAN_POWERMAGR 0xEA10
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#define KS8695_WAN_PHY_CONTROL 0xEA14
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#define KS8695_WAN_PHY_STATUS 0xEA18
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/* bus clock definitions*/
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#define KS8695_BUS_CLOCK_125MHZ 0x0
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#define KS8695_BUS_CLOCK_100MHZ 0x1
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#define KS8695_BUS_CLOCK_62MHZ 0x2
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#define KS8695_BUS_CLOCK_50MHZ 0x3
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#define KS8695_BUS_CLOCK_41MHZ 0x4
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#define KS8695_BUS_CLOCK_33MHZ 0x5
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#define KS8695_BUS_CLOCK_31MHZ 0x6
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#define KS8695_BUS_CLOCK_25MHZ 0x7
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/* -------------------------------------------------------------------------------
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* definations for IRQ
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* -------------------------------------------------------------------------------*/
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#define KS8695_INT_EXT_INT0 2
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#define KS8695_INT_EXT_INT1 3
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#define KS8695_INT_EXT_INT2 4
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#define KS8695_INT_EXT_INT3 5
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#define KS8695_INT_TIMERINT0 6
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#define KS8695_INT_TIMERINT1 7
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#define KS8695_INT_UART_TX 8
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#define KS8695_INT_UART_RX 9
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#define KS8695_INT_UART_LINE_ERR 10
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#define KS8695_INT_UART_MODEMS 11
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#define KS8695_INT_LAN_STOP_RX 12
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#define KS8695_INT_LAN_STOP_TX 13
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#define KS8695_INT_LAN_BUF_RX_STATUS 14
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#define KS8695_INT_LAN_BUF_TX_STATUS 15
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#define KS8695_INT_LAN_RX_STATUS 16
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#define KS8695_INT_LAN_TX_STATUS 17
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#define KS8695_INT_HPAN_STOP_RX 18
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#define KS8695_INT_HPNA_STOP_TX 19
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#define KS8695_INT_HPNA_BUF_RX_STATUS 20
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#define KS8695_INT_HPNA_BUF_TX_STATUS 21
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#define KS8695_INT_HPNA_RX_STATUS 22
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#define KS8695_INT_HPNA_TX_STATUS 23
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#define KS8695_INT_BUS_ERROR 24
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#define KS8695_INT_WAN_STOP_RX 25
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#define KS8695_INT_WAN_STOP_TX 26
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#define KS8695_INT_WAN_BUF_RX_STATUS 27
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#define KS8695_INT_WAN_BUF_TX_STATUS 28
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#define KS8695_INT_WAN_RX_STATUS 29
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#define KS8695_INT_WAN_TX_STATUS 30
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#define KS8695_INT_UART KS8695_INT_UART_TX
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/* -------------------------------------------------------------------------------
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* Interrupt bit positions
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*
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* -------------------------------------------------------------------------------
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*/
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#define KS8695_INTMASK_EXT_INT0 ( 1 << KS8695_INT_EXT_INT0 )
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#define KS8695_INTMASK_EXT_INT1 ( 1 << KS8695_INT_EXT_INT1 )
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#define KS8695_INTMASK_EXT_INT2 ( 1 << KS8695_INT_EXT_INT2 )
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#define KS8695_INTMASK_EXT_INT3 ( 1 << KS8695_INT_EXT_INT3 )
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#define KS8695_INTMASK_TIMERINT0 ( 1 << KS8695_INT_TIMERINT0 )
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#define KS8695_INTMASK_TIMERINT1 ( 1 << KS8695_INT_TIMERINT1 )
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#define KS8695_INTMASK_UART_TX ( 1 << KS8695_INT_UART_TX )
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#define KS8695_INTMASK_UART_RX ( 1 << KS8695_INT_UART_RX )
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#define KS8695_INTMASK_UART_LINE_ERR ( 1 << KS8695_INT_UART_LINE_ERR )
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#define KS8695_INTMASK_UART_MODEMS ( 1 << KS8695_INT_UART_MODEMS )
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#define KS8695_INTMASK_LAN_STOP_RX ( 1 << KS8695_INT_LAN_STOP_RX )
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#define KS8695_INTMASK_LAN_STOP_TX ( 1 << KS8695_INT_LAN_STOP_TX )
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#define KS8695_INTMASK_LAN_BUF_RX_STATUS ( 1 << KS8695_INT_LAN_BUF_RX_STATUS )
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#define KS8695_INTMASK_LAN_BUF_TX_STATUS ( 1 << KS8695_INT_LAN_BUF_TX_STATUS )
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#define KS8695_INTMASK_LAN_RX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
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#define KS8695_INTMASK_LAN_TX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
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#define KS8695_INTMASK_HPAN_STOP_RX ( 1 << KS8695_INT_HPAN_STOP_RX )
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#define KS8695_INTMASK_HPNA_STOP_TX ( 1 << KS8695_INT_HPNA_STOP_TX )
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#define KS8695_INTMASK_HPNA_BUF_RX_STATUS ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS )
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#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS
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#define KS8695_INTMASK_HPNA_RX_STATUS ( 1 << KS8695_INT_HPNA_RX_STATUS )
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#define KS8695_INTMASK_HPNA_TX_STATUS ( 1 << KS8695_INT_HPNA_TX_STATUS )
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#define KS8695_INTMASK_BUS_ERROR ( 1 << KS8695_INT_BUS_ERROR )
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#define KS8695_INTMASK_WAN_STOP_RX ( 1 << KS8695_INT_WAN_STOP_RX )
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#define KS8695_INTMASK_WAN_STOP_TX ( 1 << KS8695_INT_WAN_STOP_TX )
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#define KS8695_INTMASK_WAN_BUF_RX_STATUS ( 1 << KS8695_INT_WAN_BUF_RX_STATUS )
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#define KS8695_INTMASK_WAN_BUF_TX_STATUS ( 1 << KS8695_INT_WAN_BUF_TX_STATUS )
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#define KS8695_INTMASK_WAN_RX_STATUS ( 1 << KS8695_INT_WAN_RX_STATUS )
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#define KS8695_INTMASK_WAN_TX_STATUS ( 1 << KS8695_INT_WAN_TX_STATUS )
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|
|
|
||
|
|
#define KS8695_SC_VALID_INT 0xFFFFFFFF
|
||
|
|
#define MAXIRQNUM 31
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Timer definitions
|
||
|
|
*
|
||
|
|
* Use timer 1 & 2
|
||
|
|
* (both run at 25MHz).
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
#define TICKS_PER_uSEC 25
|
||
|
|
#define mSEC_1 1000
|
||
|
|
#define mSEC_10 (mSEC_1 * 10)
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* END */
|