upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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87 lines
3.3 KiB
87 lines
3.3 KiB
8 years ago
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/*
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* TV encoder driver for Allwinner SoCs.
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*
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* (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
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* (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
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* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/tve.h>
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#include <asm/io.h>
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void tvencoder_mode_set(struct sunxi_tve_reg * const tve, enum tve_mode mode)
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{
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switch (mode) {
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case tve_mode_vga:
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writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
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SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
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SUNXI_TVE_GCTRL_DAC_INPUT(2, 3), &tve->gctrl);
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writel(SUNXI_TVE_CFG0_VGA, &tve->cfg0);
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writel(SUNXI_TVE_DAC_CFG0_VGA, &tve->dac_cfg0);
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writel(SUNXI_TVE_UNKNOWN1_VGA, &tve->unknown1);
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break;
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case tve_mode_composite_pal_nc:
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writel(SUNXI_TVE_CHROMA_FREQ_PAL_NC, &tve->chroma_freq);
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/* Fall through */
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case tve_mode_composite_pal:
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writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
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SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
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SUNXI_TVE_GCTRL_DAC_INPUT(2, 3) |
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SUNXI_TVE_GCTRL_DAC_INPUT(3, 4), &tve->gctrl);
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writel(SUNXI_TVE_CFG0_PAL, &tve->cfg0);
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writel(SUNXI_TVE_DAC_CFG0_COMPOSITE, &tve->dac_cfg0);
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writel(SUNXI_TVE_FILTER_COMPOSITE, &tve->filter);
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writel(SUNXI_TVE_PORCH_NUM_PAL, &tve->porch_num);
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writel(SUNXI_TVE_LINE_NUM_PAL, &tve->line_num);
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writel(SUNXI_TVE_BLANK_BLACK_LEVEL_PAL,
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&tve->blank_black_level);
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writel(SUNXI_TVE_UNKNOWN1_COMPOSITE, &tve->unknown1);
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writel(SUNXI_TVE_CBR_LEVEL_PAL, &tve->cbr_level);
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writel(SUNXI_TVE_BURST_WIDTH_COMPOSITE, &tve->burst_width);
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writel(SUNXI_TVE_UNKNOWN2_PAL, &tve->unknown2);
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writel(SUNXI_TVE_ACTIVE_NUM_COMPOSITE, &tve->active_num);
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writel(SUNXI_TVE_CHROMA_BW_GAIN_COMP, &tve->chroma_bw_gain);
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writel(SUNXI_TVE_NOTCH_WIDTH_COMPOSITE, &tve->notch_width);
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writel(SUNXI_TVE_RESYNC_NUM_PAL, &tve->resync_num);
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writel(SUNXI_TVE_SLAVE_PARA_COMPOSITE, &tve->slave_para);
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break;
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case tve_mode_composite_pal_m:
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writel(SUNXI_TVE_CHROMA_FREQ_PAL_M, &tve->chroma_freq);
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writel(SUNXI_TVE_COLOR_BURST_PAL_M, &tve->color_burst);
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/* Fall through */
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case tve_mode_composite_ntsc:
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writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
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SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
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SUNXI_TVE_GCTRL_DAC_INPUT(2, 3) |
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SUNXI_TVE_GCTRL_DAC_INPUT(3, 4), &tve->gctrl);
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writel(SUNXI_TVE_CFG0_NTSC, &tve->cfg0);
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writel(SUNXI_TVE_DAC_CFG0_COMPOSITE, &tve->dac_cfg0);
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writel(SUNXI_TVE_FILTER_COMPOSITE, &tve->filter);
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writel(SUNXI_TVE_PORCH_NUM_NTSC, &tve->porch_num);
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writel(SUNXI_TVE_LINE_NUM_NTSC, &tve->line_num);
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writel(SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC,
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&tve->blank_black_level);
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writel(SUNXI_TVE_UNKNOWN1_COMPOSITE, &tve->unknown1);
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writel(SUNXI_TVE_CBR_LEVEL_NTSC, &tve->cbr_level);
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writel(SUNXI_TVE_BURST_PHASE_NTSC, &tve->burst_phase);
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writel(SUNXI_TVE_BURST_WIDTH_COMPOSITE, &tve->burst_width);
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writel(SUNXI_TVE_UNKNOWN2_NTSC, &tve->unknown2);
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writel(SUNXI_TVE_SYNC_VBI_LEVEL_NTSC, &tve->sync_vbi_level);
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writel(SUNXI_TVE_ACTIVE_NUM_COMPOSITE, &tve->active_num);
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writel(SUNXI_TVE_CHROMA_BW_GAIN_COMP, &tve->chroma_bw_gain);
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writel(SUNXI_TVE_NOTCH_WIDTH_COMPOSITE, &tve->notch_width);
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writel(SUNXI_TVE_RESYNC_NUM_NTSC, &tve->resync_num);
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writel(SUNXI_TVE_SLAVE_PARA_COMPOSITE, &tve->slave_para);
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break;
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}
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}
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void tvencoder_enable(struct sunxi_tve_reg * const tve)
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{
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setbits_le32(&tve->gctrl, SUNXI_TVE_GCTRL_ENABLE);
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}
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