upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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121 lines
3.5 KiB
121 lines
3.5 KiB
19 years ago
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/**
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* @file ethUtil.c
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*
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* @brief Utility functions
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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#include "IxFeatureCtrl.h"
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#include "IxEthDB_p.h"
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IX_ETH_DB_PUBLIC
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IxEthDBStatus ixEthDBSingleEthNpeCheck(IxEthDBPortId portID)
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{
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/* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */
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if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
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(ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
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|| (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
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{
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if ((portID == 0) &&
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(ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
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IX_FEATURE_CTRL_COMPONENT_DISABLED))
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{
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return IX_ETH_DB_FAIL;
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}
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if ((portID == 1) &&
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(ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
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IX_FEATURE_CTRL_COMPONENT_DISABLED))
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{
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return IX_ETH_DB_FAIL;
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}
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if ((portID == 2) &&
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(ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) ==
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IX_FEATURE_CTRL_COMPONENT_DISABLED))
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{
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return IX_ETH_DB_FAIL;
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}
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}
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return IX_ETH_DB_SUCCESS;
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}
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IX_ETH_DB_PUBLIC
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BOOL ixEthDBCheckSingleBitValue(UINT32 value)
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{
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#if (CPU != SIMSPARCSOLARIS) && !defined (__wince)
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UINT32 shift;
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/* use the count-leading-zeros XScale instruction */
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__asm__ ("clz %0, %1\n" : "=r" (shift) : "r" (value));
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return ((value << shift) == 0x80000000UL);
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#else
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while (value != 0)
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{
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if (value == 1) return TRUE;
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else if ((value & 1) == 1) return FALSE;
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value >>= 1;
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}
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return FALSE;
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#endif
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}
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const char *mac2string(const unsigned char *mac)
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{
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static char str[19];
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if (mac == NULL)
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{
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return NULL;
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}
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sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
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return str;
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}
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