upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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47 lines
1.4 KiB
47 lines
1.4 KiB
18 years ago
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/*********************************************************************
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#
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# CAUTION: This file is automatically generated by libgen.
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# Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
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# Description: U-BOOT Configuration File
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# Michal Simek - monstr@monstr.eu
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#
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**********************************************************************/
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/* System Clock Frequency */
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#define XILINX_CLOCK_FREQ 100000000
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/* Interrupt controller is opb_intc_0 */
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#define XILINX_INTC_BASEADDR 0x41200000
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#define XILINX_INTC_NUM_INTR_INPUTS 11
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/* Timer pheriphery is opb_timer_1 */
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#define XILINX_TIMER_BASEADDR 0x41c00000
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#define XILINX_TIMER_IRQ 1
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/* Uart pheriphery is RS232_Uart_1 */
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#define XILINX_UART_BASEADDR 0x40600000
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#define XILINX_UART_BAUDRATE 115200
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/* GPIO is LEDs_4Bit*/
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#define XILINX_GPIO_BASEADDR 0x40000000
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/* FLASH doesn't exist none */
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/* Main Memory is DDR_256MB_32MX64_rank1_row13_col10_cl2_5 */
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#define XILINX_RAM_START 0x30000000
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#define XILINX_RAM_SIZE 0x10000000
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/* Sysace Controller is SysACE_CompactFlash */
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#define XILINX_SYSACE_BASEADDR 0x41800000
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#define XILINX_SYSACE_HIGHADDR 0x4180ffff
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#define XILINX_SYSACE_MEM_WIDTH 16
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/* Ethernet controller is Ethernet_MAC */
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#define XPAR_XEMAC_NUM_INSTANCES 1
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#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
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#define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000
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#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff
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#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
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#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
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#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
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