Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
40145 Commits
3 Branches
0 Tags
148 MiB
Tag: Branch: Tree: 1befb38b86
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '1befb38b86'
${ noResults }
u-boot/drivers/ddr/marvell/a38x/ddr3_training_ip_centraliza...

16 lines
429 B
Raw Normal View History Unescape

arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdr This patch adds the DDR3 setup and training code taken from the Marvell U-Boot repository. This code used to be included as a binary (bin_hdr) into the Armada A38x boot image. Not linked with the main U-Boot. With this code addition and the serdes/PHY setup code, the Armada A38x support in mainline U-Boot is finally self-contained. So the complete image for booting can be built from mainline U-Boot. Without any additional external inclusion. Note: This code has undergone many hours (days!) of coding-style cleanup and refactoring. It still is not checkpatch clean though, I'm afraid. As the factoring of the code has so many levels of indentation that many lines are longer than 80 chars. Signed-off-by: Stefan Roese <sr@denx.de>
10 years ago
/*
* Copyright (C) Marvell International Ltd. and its affiliates
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _DDR3_TRAINING_IP_CENTRALIZATION_H
#define _DDR3_TRAINING_IP_CENTRALIZATION_H
int ddr3_tip_centralization_tx(u32 dev_num);
int ddr3_tip_centralization_rx(u32 dev_num);
int ddr3_tip_print_centralization_result(u32 dev_num);
int ddr3_tip_special_rx(u32 dev_num);
#endif /* _DDR3_TRAINING_IP_CENTRALIZATION_H */