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/*
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* (C) Copyright 2007-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* lwmon5.h - configuration for lwmon5 board
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_LWMON5 1 /* Board is lwmon5 */
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#define CONFIG_440EPX 1 /* Specific PPC440EPx */
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#define CONFIG_440 1 /* ... PPC440 family */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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#define CONFIG_BOARD_RESET 1 /* Call board_reset */
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
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#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
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#define CFG_BOOT_BASE_ADDR 0xf0000000
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_LIME_BASE_0 0xc0000000
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#define CFG_LIME_BASE_1 0xc1000000
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#define CFG_LIME_BASE_2 0xc2000000
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#define CFG_LIME_BASE_3 0xc3000000
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#define CFG_FPGA_BASE_0 0xc4000000
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#define CFG_FPGA_BASE_1 0xc4200000
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#define CFG_OCM_BASE 0xe0010000 /* ocm */
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#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
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#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
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#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
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#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
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#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
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/* Don't change either of these */
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#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
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#define CFG_USB2D0_BASE 0xe0000100
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#define CFG_USB_DEVICE 0xe0000000
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#define CFG_USB_HOST 0xe0000400
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer
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*----------------------------------------------------------------------*/
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/*
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* On LWMON5 we use D-cache as init-ram and stack pointer. We also move
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* the POST_WORD from OCM to a 440EPx register that preserves it's
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* content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
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* for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
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*/
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#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
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#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
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#define CFG_INIT_RAM_END (4 << 10)
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
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/* unused GPT0 COMP reg */
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ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched"
If CFG_MEM_TOP_HIDE is defined in the board config header, this specified
memory area will get subtracted from the top (end) of ram and won't get
"touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel
should gets passed the now "corrected" memory size and won't touch it
either. This should work for arch/ppc and arch/powerpc. Only Linux board
ports in arch/powerpc with bootwrapper support, which recalculate the
memory size from the SDRAM controller setup, will have to get fixed
in Linux additionally.
This patch enables this config option on some PPC440EPx boards as a workaround
for the CHIP 11 errata. Here the description from the AMCC documentation:
CHIP_11: End of memory range area restricted access.
Category: 3
Overview:
The 440EPx DDR controller does not acknowledge any
transaction which is determined to be crossing over the
end-of-memory-range boundary, even if the starting address is
within valid memory space. Any such transaction from any PLB4
master will result in a PLB time-out on PLB4 bus.
Impact:
In case of such misaligned bursts, PLB4 masters will not
retrieve any data at all, just the available data up to the
end of memory, especially the 440 CPU. For example, if a CPU
instruction required an operand located in memory within the
last 7 words of memory, the DCU master would burst read 8
words to update the data cache and cross over the
end-of-memory-range boundary. Such a DCU read would not be
answered by the DDR controller, resulting in a PLB4 time-out
and ultimately in a Machine Check interrupt. The data would
be inaccessible to the CPU.
Workaround:
Forbid any application to access the last 256 bytes of DDR
memory. For example, make your operating system believe that
the last 256 bytes of DDR memory are absent. AMCC has a patch
that does this, available for Linux.
This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards:
lwmon5, korat, sequoia
The other remaining 440EPx board were intentionally not included
since it is not clear to me, if they use the end of ram for some
other purpose. This is unclear, since these boards have CONFIG_PRAM
defined and even comments like this:
PMC440.h:
/* esd expects pram at end of physical memory.
* So no logbuffer at the moment.
*/
It is strongly recommended to not use the last 256 bytes on those
boards too. Patches from the board maintainers are welcome.
Signed-off-by: Stefan Roese <sr@denx.de>
17 years ago
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#define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
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/* 440EPx errata CHIP 11 */
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#define CFG_OCM_SIZE (16 << 10)
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/* Additional registers for watchdog timer post test */
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#define CFG_WATCHDOG_TIME_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK2)
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#define CFG_WATCHDOG_FLAGS_ADDR (CFG_PERIPHERAL_BASE + GPT0_MASK1)
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#define CFG_DSPIC_TEST_ADDR CFG_WATCHDOG_FLAGS_ADDR
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#define CFG_OCM_STATUS_ADDR CFG_WATCHDOG_FLAGS_ADDR
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#define CFG_WATCHDOG_MAGIC 0x12480000
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#define CFG_WATCHDOG_MAGIC_MASK 0xFFFF0000
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#define CFG_DSPIC_TEST_MASK 0x00000001
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#define CFG_OCM_STATUS_OK 0x00009A00
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#define CFG_OCM_STATUS_FAIL 0x0000A300
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#define CFG_OCM_STATUS_MASK 0x0000FF00
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#undef CFG_EXT_SERIAL_CLOCK /* no external clock provided */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SERIAL_MULTI 1
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/* define this if you want console on UART1 */
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#define CONFIG_UART1_CONSOLE 1 /* use UART1 as console */
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CFG_FLASH0 0xFC000000
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#define CFG_FLASH1 0xF8000000
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#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
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#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
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#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
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#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CFG_MBYTES_SDRAM (256) /* 256MB */
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#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
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#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
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#define CONFIG_DDR_ECC 1 /* enable ECC */
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#define CFG_POST_ECC_ON CFG_POST_ECC
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/* POST support */
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#define CONFIG_POST (CFG_POST_CACHE | \
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CFG_POST_CPU | \
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CFG_POST_ECC_ON | \
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CFG_POST_ETHER | \
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CFG_POST_FPU | \
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CFG_POST_I2C | \
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CFG_POST_MEMORY | \
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CFG_POST_OCM | \
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CFG_POST_RTC | \
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CFG_POST_SPR | \
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CFG_POST_UART | \
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CFG_POST_SYSMON | \
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CFG_POST_WATCHDOG | \
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CFG_POST_DSP | \
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CFG_POST_BSPEC1 | \
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CFG_POST_BSPEC2 | \
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CFG_POST_BSPEC3 | \
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CFG_POST_BSPEC4 | \
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CFG_POST_BSPEC5)
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#define CONFIG_POST_WATCHDOG {\
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"Watchdog timer test", \
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"watchdog", \
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"This test checks the watchdog timer.", \
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POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
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&lwmon5_watchdog_post_test, \
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NULL, \
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NULL, \
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CFG_POST_WATCHDOG \
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}
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#define CONFIG_POST_BSPEC1 {\
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"dsPIC init test", \
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"dspic_init", \
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"This test returns result of dsPIC READY test run earlier.", \
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POST_RAM | POST_ALWAYS, \
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&dspic_init_post_test, \
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NULL, \
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NULL, \
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CFG_POST_BSPEC1 \
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}
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#define CONFIG_POST_BSPEC2 {\
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"dsPIC test", \
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"dspic", \
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"This test gets result of dsPIC POST and dsPIC version.", \
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POST_RAM | POST_ALWAYS, \
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&dspic_post_test, \
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NULL, \
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NULL, \
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CFG_POST_BSPEC2 \
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}
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#define CONFIG_POST_BSPEC3 {\
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"FPGA test", \
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"fpga", \
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"This test checks FPGA registers and memory.", \
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POST_RAM | POST_ALWAYS, \
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&fpga_post_test, \
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NULL, \
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NULL, \
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CFG_POST_BSPEC3 \
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}
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#define CONFIG_POST_BSPEC4 {\
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"GDC test", \
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"gdc", \
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"This test checks GDC registers and memory.", \
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POST_RAM | POST_ALWAYS, \
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&gdc_post_test, \
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NULL, \
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NULL, \
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CFG_POST_BSPEC4 \
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}
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#define CONFIG_POST_BSPEC5 {\
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"SYSMON1 test", \
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"sysmon1", \
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"This test checks GPIO_62_EPX pin indicating power failure.", \
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POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
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&sysmon1_post_test, \
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NULL, \
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NULL, \
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CFG_POST_BSPEC5 \
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}
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#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
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#define CONFIG_LOGBUFFER
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/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
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#define CONFIG_ALT_LH_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP1)
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#define CONFIG_ALT_LB_ADDR (CFG_OCM_BASE)
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#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */
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#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
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#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
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/* 64 byte page write mode using*/
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/* last 6 bits of the address */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
|
|
|
|
|
#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
|
|
|
|
|
#define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
|
|
|
|
|
#define CFG_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
|
|
|
|
|
|
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|
|
|
#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
|
|
|
|
|
#if 0
|
|
|
|
|
#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
|
|
|
|
|
#define CONFIG_AUTOBOOT_PROMPT \
|
|
|
|
|
"\nEnter password - autoboot in %d sec...\n", bootdelay
|
|
|
|
|
#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#define CONFIG_PREBOOT "setenv bootdelay 15"
|
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|
|
|
|
#undef CONFIG_BOOTARGS
|
|
|
|
|
|
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
|
|
|
"hostname=lwmon5\0" \
|
|
|
|
|
"netdev=eth0\0" \
|
|
|
|
|
"unlock=yes\0" \
|
|
|
|
|
"logversion=2\0" \
|
|
|
|
|
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
|
|
|
|
"nfsroot=${serverip}:${rootpath}\0" \
|
|
|
|
|
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
|
|
|
|
"addip=setenv bootargs ${bootargs} " \
|
|
|
|
|
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
|
|
|
|
":${hostname}:${netdev}:off panic=1\0" \
|
|
|
|
|
"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
|
|
|
|
|
"addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
|
|
|
|
|
"flash_nfs=run nfsargs addip addtty addmisc;" \
|
|
|
|
|
"bootm ${kernel_addr}\0" \
|
|
|
|
|
"flash_self=run ramargs addip addtty addmisc;" \
|
|
|
|
|
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
|
|
|
|
"net_nfs=tftp 200000 ${bootfile};" \
|
|
|
|
|
"run nfsargs addip addtty addmisc;bootm\0" \
|
|
|
|
|
"rootpath=/opt/eldk/ppc_4xxFP\0" \
|
|
|
|
|
"bootfile=/tftpboot/lwmon5/uImage\0" \
|
|
|
|
|
"kernel_addr=FC000000\0" \
|
|
|
|
|
"ramdisk_addr=FC180000\0" \
|
|
|
|
|
"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
|
|
|
|
|
"update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
|
|
|
|
|
"cp.b 200000 FFF80000 80000\0" \
|
|
|
|
|
"upd=run load update\0" \
|
|
|
|
|
"lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
|
|
|
|
|
"autoscr 200000\0" \
|
|
|
|
|
""
|
|
|
|
|
#define CONFIG_BOOTCOMMAND "run flash_self"
|
|
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
|
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
|
|
|
|
#else
|
|
|
|
|
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
|
|
|
|
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
|
|
|
|
|
|
|
|
|
#define CONFIG_IBM_EMAC4_V4 1
|
|
|
|
|
#define CONFIG_MII 1 /* MII PHY management */
|
|
|
|
|
#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
|
|
|
|
|
|
|
|
|
|
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
|
|
|
|
|
#define CONFIG_PHY_RESET_DELAY 300
|
|
|
|
|
|
|
|
|
|
#define CONFIG_HAS_ETH0
|
|
|
|
|
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
|
|
|
|
|
|
|
|
|
|
#define CONFIG_NET_MULTI 1
|
|
|
|
|
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
|
|
|
|
|
#define CONFIG_PHY1_ADDR 1
|
|
|
|
|
|
|
|
|
|
/* Video console */
|
|
|
|
|
#define CONFIG_VIDEO
|
|
|
|
|
#define CONFIG_VIDEO_MB862xx
|
|
|
|
|
#define CONFIG_CFB_CONSOLE
|
|
|
|
|
#define CONFIG_VIDEO_LOGO
|
|
|
|
|
#define CONFIG_CONSOLE_EXTRA_INFO
|
|
|
|
|
#define VIDEO_FB_16BPP_PIXEL_SWAP
|
|
|
|
|
|
|
|
|
|
#define CONFIG_VGA_AS_SINGLE_DEVICE
|
|
|
|
|
#define CONFIG_VIDEO_SW_CURSOR
|
|
|
|
|
#define CONFIG_SPLASH_SCREEN
|
|
|
|
|
|
|
|
|
|
/* USB */
|
|
|
|
|
#ifdef CONFIG_440EPX
|
|
|
|
|
#define CONFIG_USB_OHCI
|
|
|
|
|
#define CONFIG_USB_STORAGE
|
|
|
|
|
|
|
|
|
|
/* Comment this out to enable USB 1.1 device */
|
|
|
|
|
#define USB_2_0_DEVICE
|
|
|
|
|
|
|
|
|
|
#endif /* CONFIG_440EPX */
|
|
|
|
|
|
|
|
|
|
/* Partitions */
|
|
|
|
|
#define CONFIG_MAC_PARTITION
|
|
|
|
|
#define CONFIG_DOS_PARTITION
|
|
|
|
|
#define CONFIG_ISO_PARTITION
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* BOOTP options
|
|
|
|
|
*/
|
|
|
|
|
#define CONFIG_BOOTP_BOOTFILESIZE
|
|
|
|
|
#define CONFIG_BOOTP_BOOTPATH
|
|
|
|
|
#define CONFIG_BOOTP_GATEWAY
|
|
|
|
|
#define CONFIG_BOOTP_HOSTNAME
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Command line configuration.
|
|
|
|
|
*/
|
|
|
|
|
#include <config_cmd_default.h>
|
|
|
|
|
|
|
|
|
|
#define CONFIG_CMD_ASKENV
|
|
|
|
|
#define CONFIG_CMD_DATE
|
|
|
|
|
#define CONFIG_CMD_DHCP
|
|
|
|
|
#define CONFIG_CMD_DIAG
|
|
|
|
|
#define CONFIG_CMD_EEPROM
|
|
|
|
|
#define CONFIG_CMD_ELF
|
|
|
|
|
#define CONFIG_CMD_FAT
|
|
|
|
|
#define CONFIG_CMD_I2C
|
|
|
|
|
#define CONFIG_CMD_IRQ
|
|
|
|
|
#define CONFIG_CMD_LOG
|
|
|
|
|
#define CONFIG_CMD_MII
|
|
|
|
|
#define CONFIG_CMD_NET
|
|
|
|
|
#define CONFIG_CMD_NFS
|
|
|
|
|
#define CONFIG_CMD_PCI
|
|
|
|
|
#define CONFIG_CMD_PING
|
|
|
|
|
#define CONFIG_CMD_REGINFO
|
|
|
|
|
#define CONFIG_CMD_SDRAM
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_VIDEO
|
|
|
|
|
#define CONFIG_CMD_BMP
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_440EPX
|
|
|
|
|
#define CONFIG_CMD_USB
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/*-----------------------------------------------------------------------
|
|
|
|
|
* Miscellaneous configurable options
|
|
|
|
|
*----------------------------------------------------------------------*/
|
|
|
|
|
#define CONFIG_SUPPORT_VFAT
|
|
|
|
|
|
|
|
|
|
#define CFG_LONGHELP /* undef to save memory */
|
|
|
|
|
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
|
|
|
|
|
|
|
|
|
#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
|
|
|
|
|
#ifdef CFG_HUSH_PARSER
|
|
|
|
|
#define CFG_PROMPT_HUSH_PS2 "> "
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
|
|
|
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
|
|
|
|
#else
|
|
|
|
|
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
|
|
|
|
#endif
|
|
|
|
|
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
|
|
|
|
#define CFG_MAXARGS 16 /* max number of command args */
|
|
|
|
|
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
|
|
|
|
|
|
|
|
|
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
|
|
|
|
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
|
|
|
|
|
|
|
|
|
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
|
|
|
|
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
|
|
|
|
|
|
|
|
|
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
|
|
|
|
|
|
|
|
|
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
|
|
|
|
#define CONFIG_LOOPW 1 /* enable loopw command */
|
|
|
|
|
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
|
|
|
|
|
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
|
|
|
|
|
|
|
|
|
/*-----------------------------------------------------------------------
|
|
|
|
|
* PCI stuff
|
|
|
|
|
*----------------------------------------------------------------------*/
|
|
|
|
|
/* General PCI */
|
|
|
|
|
#define CONFIG_PCI /* include pci support */
|
|
|
|
|
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
|
|
|
|
|
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
|
|
|
|
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
|
|
|
|
|
|
|
|
|
|
/* Board-specific PCI */
|
|
|
|
|
#define CFG_PCI_TARGET_INIT
|
|
|
|
|
#define CFG_PCI_MASTER_INIT
|
|
|
|
|
|
|
|
|
|
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
|
|
|
|
|
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
|
|
|
|
|
|
|
|
|
|
#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
|
|
|
|
|
#define CONFIG_WD_PERIOD 40000 /* in usec */
|
|
|
|
|
#define CONFIG_WD_MAX_RATE 66600 /* in ticks */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* For booting Linux, the board info and command line data
|
|
|
|
|
* have to be in the first 8 MB of memory, since this is
|
|
|
|
|
* the maximum mapped by the Linux kernel during initialization.
|
|
|
|
|
*/
|
|
|
|
|
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
|
|
|
|
|
|
|
|
|
/*-----------------------------------------------------------------------
|
|
|
|
|
* External Bus Controller (EBC) Setup
|
|
|
|
|
*----------------------------------------------------------------------*/
|
|
|
|
|
#define CFG_FLASH CFG_FLASH_BASE
|
|
|
|
|
|
|
|
|
|
/* Memory Bank 0 (NOR-FLASH) initialization */
|
|
|
|
|
#define CFG_EBC_PB0AP 0x03050200
|
|
|
|
|
#define CFG_EBC_PB0CR (CFG_FLASH | 0xfc000)
|
|
|
|
|
|
|
|
|
|
/* Memory Bank 1 (Lime) initialization */
|
|
|
|
|
#define CFG_EBC_PB1AP 0x01004380
|
|
|
|
|
#define CFG_EBC_PB1CR (CFG_LIME_BASE_0 | 0xdc000)
|
|
|
|
|
|
|
|
|
|
/* Memory Bank 2 (FPGA) initialization */
|
|
|
|
|
#define CFG_EBC_PB2AP 0x01004400
|
|
|
|
|
#define CFG_EBC_PB2CR (CFG_FPGA_BASE_0 | 0x1c000)
|
|
|
|
|
|
|
|
|
|
/* Memory Bank 3 (FPGA2) initialization */
|
|
|
|
|
#define CFG_EBC_PB3AP 0x01004400
|
|
|
|
|
#define CFG_EBC_PB3CR (CFG_FPGA_BASE_1 | 0x1c000)
|
|
|
|
|
|
|
|
|
|
#define CFG_EBC_CFG 0xb8400000
|
|
|
|
|
|
|
|
|
|
/*-----------------------------------------------------------------------
|
|
|
|
|
* Graphics (Fujitsu Lime)
|
|
|
|
|
*----------------------------------------------------------------------*/
|
|
|
|
|
/* SDRAM Clock frequency adjustment register */
|
|
|
|
|
#define CFG_LIME_SDRAM_CLOCK 0xC1FC0038
|
|
|
|
|
/* Lime Clock frequency is to set 100MHz */
|
|
|
|
|
#define CFG_LIME_CLOCK_100MHZ 0x00000
|
|
|
|
|
#if 0
|
|
|
|
|
/* Lime Clock frequency for 133MHz */
|
|
|
|
|
#define CFG_LIME_CLOCK_133MHZ 0x10000
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* SDRAM Parameter register */
|
|
|
|
|
#define CFG_LIME_MMR 0xC1FCFFFC
|
|
|
|
|
/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
|
|
|
|
|
and pixel flare on display when 133MHz was configured. According to
|
|
|
|
|
SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
|
|
|
|
|
#ifdef CFG_LIME_CLOCK_133MHZ
|
|
|
|
|
#define CFG_LIME_MMR_VALUE 0x414FB7F3
|
|
|
|
|
#else
|
|
|
|
|
#define CFG_LIME_MMR_VALUE 0x414FB7F2
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/*-----------------------------------------------------------------------
|
|
|
|
|
* GPIO Setup
|
|
|
|
|
*----------------------------------------------------------------------*/
|
|
|
|
|
#define CFG_GPIO_PHY1_RST 12
|
|
|
|
|
#define CFG_GPIO_FLASH_WP 14
|
|
|
|
|
#define CFG_GPIO_PHY0_RST 22
|
|
|
|
|
#define CFG_GPIO_DSPIC_READY 51
|
|
|
|
|
#define CFG_GPIO_EEPROM_EXT_WP 55
|
|
|
|
|
#define CFG_GPIO_HIGHSIDE 56
|
|
|
|
|
#define CFG_GPIO_EEPROM_INT_WP 57
|
|
|
|
|
#define CFG_GPIO_BOARD_RESET 58
|
|
|
|
|
#define CFG_GPIO_LIME_S 59
|
|
|
|
|
#define CFG_GPIO_LIME_RST 60
|
|
|
|
|
#define CFG_GPIO_SYSMON_STATUS 62
|
|
|
|
|
#define CFG_GPIO_WATCHDOG 63
|
|
|
|
|
|
|
|
|
|
/*-----------------------------------------------------------------------
|
|
|
|
|
* PPC440 GPIO Configuration
|
|
|
|
|
*/
|
|
|
|
|
#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
|
|
|
|
|
{ \
|
|
|
|
|
/* GPIO Core 0 */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
|
|
|
|
|
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
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}, \
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{ \
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/* GPIO Core 1 */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
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{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
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{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
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{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
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} \
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}
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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#endif /* __CONFIG_H */
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