upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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186 lines
5.4 KiB
186 lines
5.4 KiB
22 years ago
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/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#if defined(CONFIG_MGT5100)
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#define START_REG(start) ((start) >> 15)
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#define STOP_REG(start, size) (((start) + (size) - 1) >> 15)
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#elif defined(CONFIG_MPC5200)
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#define START_REG(start) ((start) >> 16)
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#define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
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#endif
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers.
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*/
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void cpu_init_f (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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unsigned long addecr = (1 << 25); /* Boot_CS */
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#if defined(CFG_RAMBOOT) && defined(CONFIG_MGT5100)
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addecr |= (1 << 22); /* SDRAM enable */
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#endif
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
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/* Clear initial global data */
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memset ((void *) gd, 0, sizeof (gd_t));
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/*
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* Memory Controller: configure chip selects and enable them
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*/
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#if defined(CFG_BOOTCS_START) && defined(CFG_BOOTCS_SIZE)
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*(vu_long *)MPC5XXX_BOOTCS_START = START_REG(CFG_BOOTCS_START);
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*(vu_long *)MPC5XXX_BOOTCS_STOP = STOP_REG(CFG_BOOTCS_START,
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CFG_BOOTCS_SIZE);
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#endif
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#if defined(CFG_BOOTCS_CFG)
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*(vu_long *)MPC5XXX_BOOTCS_CFG = CFG_BOOTCS_CFG;
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#endif
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#if defined(CFG_CS0_START) && defined(CFG_CS0_SIZE)
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*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_CS0_START);
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*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_CS0_START, CFG_CS0_SIZE);
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/* CS0 and BOOT_CS cannot be enabled at once. */
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/* addecr |= (1 << 16); */
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#endif
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#if defined(CFG_CS0_CFG)
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*(vu_long *)MPC5XXX_CS0_CFG = CFG_CS0_CFG;
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#endif
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#if defined(CFG_CS1_START) && defined(CFG_CS1_SIZE)
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*(vu_long *)MPC5XXX_CS1_START = START_REG(CFG_CS1_START);
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*(vu_long *)MPC5XXX_CS1_STOP = STOP_REG(CFG_CS1_START, CFG_CS1_SIZE);
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addecr |= (1 << 17);
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#endif
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#if defined(CFG_CS1_CFG)
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*(vu_long *)MPC5XXX_CS1_CFG = CFG_CS1_CFG;
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#endif
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#if defined(CFG_CS2_START) && defined(CFG_CS2_SIZE)
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*(vu_long *)MPC5XXX_CS2_START = START_REG(CFG_CS2_START);
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*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, CFG_CS2_SIZE);
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addecr |= (1 << 18);
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#endif
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#if defined(CFG_CS2_CFG)
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*(vu_long *)MPC5XXX_CS2_CFG = CFG_CS2_CFG;
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#endif
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#if defined(CFG_CS3_START) && defined(CFG_CS3_SIZE)
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*(vu_long *)MPC5XXX_CS3_START = START_REG(CFG_CS3_START);
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*(vu_long *)MPC5XXX_CS3_STOP = STOP_REG(CFG_CS3_START, CFG_CS3_SIZE);
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addecr |= (1 << 19);
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#endif
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#if defined(CFG_CS3_CFG)
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*(vu_long *)MPC5XXX_CS3_CFG = CFG_CS3_CFG;
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#endif
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#if defined(CFG_CS4_START) && defined(CFG_CS4_SIZE)
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*(vu_long *)MPC5XXX_CS4_START = START_REG(CFG_CS4_START);
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*(vu_long *)MPC5XXX_CS4_STOP = STOP_REG(CFG_CS4_START, CFG_CS4_SIZE);
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addecr |= (1 << 20);
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#endif
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#if defined(CFG_CS4_CFG)
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*(vu_long *)MPC5XXX_CS4_CFG = CFG_CS4_CFG;
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#endif
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#if defined(CFG_CS5_START) && defined(CFG_CS5_SIZE)
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*(vu_long *)MPC5XXX_CS5_START = START_REG(CFG_CS5_START);
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*(vu_long *)MPC5XXX_CS5_STOP = STOP_REG(CFG_CS5_START, CFG_CS5_SIZE);
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addecr |= (1 << 21);
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#endif
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#if defined(CFG_CS5_CFG)
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*(vu_long *)MPC5XXX_CS5_CFG = CFG_CS5_CFG;
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#endif
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#if defined(CONFIG_MPC5200)
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addecr |= 1;
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#if defined(CFG_CS6_START) && defined(CFG_CS6_SIZE)
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*(vu_long *)MPC5XXX_CS6_START = START_REG(CFG_CS6_START);
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*(vu_long *)MPC5XXX_CS6_STOP = STOP_REG(CFG_CS6_START, CFG_CS6_SIZE);
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addecr |= (1 << 26);
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#endif
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#if defined(CFG_CS6_CFG)
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*(vu_long *)MPC5XXX_CS6_CFG = CFG_CS6_CFG;
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#endif
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#if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE)
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*(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS5_START);
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*(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE);
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addecr |= (1 << 27);
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#endif
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#if defined(CFG_CS7_CFG)
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*(vu_long *)MPC5XXX_CS7_CFG = CFG_CS7_CFG;
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#endif
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#if defined(CFG_CS_BURST)
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*(vu_long *)MPC5XXX_CS_BURST = CFG_CS_BURST;
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#endif
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#if defined(CFG_CS_DEADCYCLE)
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*(vu_long *)MPC5XXX_CS_DEADCYCLE = CFG_CS_DEADCYCLE;
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#endif
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#endif /* CONFIG_MPC5200 */
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/* Enable chip selects */
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*(vu_long *)MPC5XXX_ADDECR = addecr;
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*(vu_long *)MPC5XXX_CS_CTRL = (1 << 24);
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/* Setup pin multiplexing */
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#if defined(CFG_GPS_PORT_CONFIG)
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*(vu_long *)MPC5XXX_GPS_PORT_CONFIG = CFG_GPS_PORT_CONFIG;
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#endif
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}
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/*
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* initialize higher level parts of CPU like time base and timers
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*/
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int cpu_init_r (void)
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{
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/* mask all interrupts */
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#if defined(CONFIG_MGT5100)
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*(vu_long *)MPC5XXX_ICTL_PER_MASK = 0xfffffc00;
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#elif defined(CONFIG_MPC5200)
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*(vu_long *)MPC5XXX_ICTL_PER_MASK = 0xffffff00;
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#endif
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*(vu_long *)MPC5XXX_ICTL_CRIT |= 0x0001ffff;
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*(vu_long *)MPC5XXX_ICTL_EXT &= ~0x00000f00;
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#if defined(CONFIG_MPC5200)
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/* enable timebase */
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*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13);
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#endif
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#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC5XXX_FEC)
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/* load FEC microcode */
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loadtask(0, 2);
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#endif
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return (0);
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}
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