u-boot/arch/arm/mach-zynq/include/mach/clk.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (c) 2013 Xilinx Inc.
 */

#ifndef _ZYNQ_CLK_H_
#define _ZYNQ_CLK_H_

enum zynq_clk {
	armpll_clk, ddrpll_clk, iopll_clk,
	cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk,
	ddr2x_clk, ddr3x_clk, dci_clk,
	lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk,
	fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk,
	sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk,
	usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk,
	sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk,
	can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk,
	uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk,
	smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max};

#endif
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> 7 years ago			`/* SPDX-License-Identifier: GPL-2.0+ */`
zynq: Provide a framework to read clock frequencies Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 11 years ago			`/*`
			`* Copyright (c) 2013 Xilinx Inc.`
			`*/`

			`#ifndef _ZYNQ_CLK_H_`
			`#define _ZYNQ_CLK_H_`

			`enum zynq_clk {`
			`armpll_clk, ddrpll_clk, iopll_clk,`
			`cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk,`
			`ddr2x_clk, ddr3x_clk, dci_clk,`
			`lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk,`
			`fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk,`
			`sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk,`
			`usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk,`
			`sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk,`
			`can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk,`
			`uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk,`
			`smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max};`

			`#endif`