upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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114 lines
4.4 KiB
114 lines
4.4 KiB
22 years ago
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/* PCI.h - PCI functions header file */
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/* Copyright - Galileo technology. */
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#ifndef __INCpcih
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#define __INCpcih
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/* includes */
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#include "core.h"
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#include "memory.h"
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/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
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#define PCI_MAX_DEVICES 22
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/* Macros */
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#define SELF 32
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/* Defines for the access regions. */
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#define PREFETCH_ENABLE BIT12
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#define PREFETCH_DISABLE NO_BIT
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#define DELAYED_READ_ENABLE BIT13
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/* #define CACHING_ENABLE BIT14 */
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/* aggressive prefetch: PCI slave prefetch two burst in advance*/
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#define AGGRESSIVE_PREFETCH BIT16
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/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
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#define READ_LINE_AGGRESSIVE_PREFETCH BIT17
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/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
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#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18
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#define MAX_BURST_4 NO_BIT
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#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */
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#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */
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#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */
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#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */
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#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */
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#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */
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#define PCI_ACCESS_PROTECT BIT28
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#define PCI_WRITE_PROTECT BIT29
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/* typedefs */
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typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
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REGION6,REGION7} PCI_ACCESS_REGIONS;
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typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
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typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
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typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
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PCI_SNOOP_TYPE;
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typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
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PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
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PCI_SNOOP_REGION;
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typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
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typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
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PCI_REGION2,PCI_REGION3,
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PCI_IO}
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PCI_REGION;
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/* read/write configuration registers on local PCI bus. */
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void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
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unsigned int pciDevNum, unsigned int data);
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unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
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unsigned int pciDevNum);
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/* read/write configuration registers on another PCI bus. */
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void pciOverBridgeWriteConfigReg(PCI_HOST host,
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unsigned int regOffset,
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unsigned int pciDevNum,
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unsigned int busNum,unsigned int data);
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unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
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unsigned int regOffset,
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unsigned int pciDevNum,
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unsigned int busNum);
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/* Master`s memory space */
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bool pciMapSpace(PCI_HOST host, PCI_REGION region,
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unsigned int remapBase,
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unsigned int deviceBase,
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unsigned int deviceLength);
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unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
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unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
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/* Slave`s memory space */
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void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
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unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
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/* PCI region options */
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bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
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unsigned int features, unsigned int baseAddress,
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unsigned int regionLength);
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void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
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/* PCI arbiter */
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bool pciArbiterEnable(PCI_HOST host);
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bool pciArbiterDisable(PCI_HOST host);
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bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
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PCI_AGENT_PARK externalAgent0,
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PCI_AGENT_PARK externalAgent1,
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PCI_AGENT_PARK externalAgent2,
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PCI_AGENT_PARK externalAgent3,
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PCI_AGENT_PARK externalAgent4,
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PCI_AGENT_PARK externalAgent5);
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bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
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PCI_SNOOP_TYPE snoopType,
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unsigned int baseAddress,
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unsigned int regionLength);
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#endif /* __INCpcih */
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