upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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30 lines
958 B
30 lines
958 B
6 years ago
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Texas Instruments TI SCI System Reset Controller
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================================================
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Some TI SoCs contain a system controller (like the SYSFW, etc...) that is
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responsible for controlling the state of the IPs that are present.
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Communication between the host processor running an OS and the system
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controller happens through a protocol known as TI SCI [1].
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[1] http://processors.wiki.ti.com/index.php/TISCI
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System Reset Controller Node
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============================
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The sysreset controller node represents the reset for the overall SoC
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which is managed by the SYSFW. Because this relies on the TI SCI protocol
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to communicate with the SYSFW it must be a child of the sysfw node.
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Required Properties:
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--------------------
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- compatible: Must be "ti,sci-sysreset"
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Example (AM65x):
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----------------
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sysfw: sysfw {
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compatible = "ti,am654-system-controller";
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...
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k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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};
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};
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