upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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84 lines
2.8 KiB
84 lines
2.8 KiB
14 years ago
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/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __BOARD_MX35_3STACK_H
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#define __BOARD_MX35_3STACK_H
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#define AIPS_MPR_CONFIG 0x77777777
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#define AIPS_OPACR_CONFIG 0x00000000
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/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
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#define MAX_MPR_CONFIG 0x00302154
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/* SGPCR - always park on last master */
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#define MAX_SGPCR_CONFIG 0x00000010
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/* MGPCR - restore default values */
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#define MAX_MGPCR_CONFIG 0x00000000
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/*
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* M3IF Control Register (M3IFCTL)
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* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
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* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
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* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
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* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
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* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
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* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
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* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
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* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
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* ------------
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* 0x00000040
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*/
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#define M3IF_CONFIG 0x00000040
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#define DBG_BASE_ADDR WEIM_CTRL_CS5
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#define DBG_CSCR_U_CONFIG 0x0000D843
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#define DBG_CSCR_L_CONFIG 0x22252521
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#define DBG_CSCR_A_CONFIG 0x22220A00
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#define CCM_CCMR_CONFIG 0x003F4208
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#define CCM_PDR0_CONFIG 0x00801000
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/* MEMORY SETTING */
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#define ESDCTL_0x92220000 0x92220000
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#define ESDCTL_0xA2220000 0xA2220000
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#define ESDCTL_0xB2220000 0xB2220000
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#define ESDCTL_0x82228080 0x82228080
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#define ESDCTL_PRECHARGE 0x00000400
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#define ESDCTL_MDDR_CONFIG 0x007FFC3F
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#define ESDCTL_MDDR_MR 0x00000033
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#define ESDCTL_MDDR_EMR 0x02000000
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#define ESDCTL_DDR2_CONFIG 0x007FFC3F
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#define ESDCTL_DDR2_EMR2 0x04000000
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#define ESDCTL_DDR2_EMR3 0x06000000
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#define ESDCTL_DDR2_EN_DLL 0x02000400
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#define ESDCTL_DDR2_RESET_DLL 0x00000333
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#define ESDCTL_DDR2_MR 0x00000233
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#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
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#define ESDCTL_DELAY_LINE5 0x00F49F00
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#endif /* __BOARD_MX35_3STACK_H */
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