upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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213 lines
3.2 KiB
213 lines
3.2 KiB
8 years ago
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/*
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* dts file for Xilinx ZynqMP zc1751-xm018-dc4
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*
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* (C) Copyright 2015 - 2016, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk.dtsi"
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/ {
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model = "ZynqMP zc1751-xm018-dc4";
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compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
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aliases {
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can0 = &can0;
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can1 = &can1;
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ethernet0 = &gem0;
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ethernet1 = &gem1;
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ethernet2 = &gem2;
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ethernet3 = &gem3;
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gpio0 = &gpio;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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rtc0 = &rtc;
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serial0 = &uart0;
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serial1 = &uart1;
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spi0 = &qspi;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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};
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&can0 {
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status = "okay";
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};
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&can1 {
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status = "okay";
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};
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/* fpd_dma clk 667MHz, lpd_dma 500MHz */
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&fpd_dma_chan1 {
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status = "okay";
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xlnx,include-sg; /* for testing purpose */
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xlnx,overfetch; /* for testing purpose */
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xlnx,ratectrl = <0>; /* for testing purpose */
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xlnx,src-issue = <31>;
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};
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&fpd_dma_chan2 {
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status = "okay";
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xlnx,ratectrl = <100>; /* for testing purpose */
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xlnx,src-issue = <4>; /* for testing purpose */
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};
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&fpd_dma_chan3 {
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status = "okay";
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};
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&fpd_dma_chan4 {
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status = "okay";
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xlnx,include-sg; /* for testing purpose */
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};
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&fpd_dma_chan5 {
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status = "okay";
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};
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&fpd_dma_chan6 {
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status = "okay";
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xlnx,include-sg; /* for testing purpose */
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};
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&fpd_dma_chan7 {
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status = "okay";
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};
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&fpd_dma_chan8 {
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status = "okay";
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xlnx,include-sg; /* for testing purpose */
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};
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&lpd_dma_chan1 {
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status = "okay";
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};
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&lpd_dma_chan2 {
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status = "okay";
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};
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&lpd_dma_chan3 {
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status = "okay";
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};
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&lpd_dma_chan4 {
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status = "okay";
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};
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&lpd_dma_chan5 {
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status = "okay";
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};
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&lpd_dma_chan6 {
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status = "okay";
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};
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&lpd_dma_chan7 {
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status = "okay";
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};
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&lpd_dma_chan8 {
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status = "okay";
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};
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&xlnx_dp {
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status = "okay";
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};
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&xlnx_dpdma {
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status = "okay";
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};
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&gem0 {
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status = "okay";
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local-mac-address = [00 0a 35 00 02 90];
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy0>;
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ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
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reg = <0>;
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};
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ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
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reg = <7>;
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};
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ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
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reg = <3>;
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};
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ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
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reg = <8>;
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};
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};
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&gem1 {
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status = "okay";
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local-mac-address = [00 0a 35 00 02 91];
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy7>;
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};
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&gem2 {
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status = "okay";
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local-mac-address = [00 0a 35 00 02 92];
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy3>;
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};
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&gem3 {
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status = "okay";
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local-mac-address = [00 0a 35 00 02 93];
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy8>;
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};
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&gpio {
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status = "okay";
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};
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&gpu {
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status = "okay";
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};
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&i2c0 {
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clock-frequency = <400000>;
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <400000>;
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status = "okay";
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};
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&rtc {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&watchdog0 {
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status = "okay";
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};
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