upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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61 lines
1.3 KiB
61 lines
1.3 KiB
10 years ago
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/*
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* Copyright (c) 2015, Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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* All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <errno.h>
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#include <pci.h>
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#include <usb.h>
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#include "xhci.h"
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/*
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* Create the appropriate control structures to manage a new XHCI host
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* controller.
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*/
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int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
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struct xhci_hcor **ret_hcor)
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{
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struct xhci_hccr *hccr;
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struct xhci_hcor *hcor;
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pci_dev_t pdev;
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uint32_t cmd;
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int len;
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pdev = pci_find_class(PCI_CLASS_SERIAL_USB_XHCI, index);
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if (pdev < 0) {
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printf("XHCI host controller not found\n");
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return -1;
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}
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hccr = (struct xhci_hccr *)pci_map_bar(pdev,
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PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
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len = HC_LENGTH(xhci_readl(&hccr->cr_capbase));
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hcor = (struct xhci_hcor *)((uint32_t)hccr + len);
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debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
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(uint32_t)hccr, (uint32_t)hcor, len);
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*ret_hccr = hccr;
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*ret_hcor = hcor;
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/* enable busmaster */
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pci_read_config_dword(pdev, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_MASTER;
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pci_write_config_dword(pdev, PCI_COMMAND, cmd);
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return 0;
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}
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/*
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* Destroy the appropriate control structures corresponding * to the XHCI host
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* controller
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*/
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void xhci_hcd_stop(int index)
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{
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}
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