upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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133 lines
4.8 KiB
133 lines
4.8 KiB
19 years ago
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/*
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <ppc_asm.tmpl>
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#include <config.h>
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/* General */
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#define TLB_VALID 0x00000200
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/* Supported page sizes */
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#define SZ_1K 0x00000000
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#define SZ_4K 0x00000010
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#define SZ_16K 0x00000020
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#define SZ_64K 0x00000030
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#define SZ_256K 0x00000040
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#define SZ_1M 0x00000050
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#define SZ_16M 0x00000070
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#define SZ_256M 0x00000090
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/* Storage attributes */
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#define SA_W 0x00000800 /* Write-through */
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#define SA_I 0x00000400 /* Caching inhibited */
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#define SA_M 0x00000200 /* Memory coherence */
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#define SA_G 0x00000100 /* Guarded */
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#define SA_E 0x00000080 /* Endian */
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/* Access control */
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#define AC_X 0x00000024 /* Execute */
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#define AC_W 0x00000012 /* Write */
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#define AC_R 0x00000009 /* Read */
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/* Some handy macros */
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#define EPN(e) ((e) & 0xfffffc00)
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#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
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#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
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#define TLB2(a) ( (a)&0x00000fbf )
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#define tlbtab_start\
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mflr r1 ;\
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bl 0f ;
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#define tlbtab_end\
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.long 0, 0, 0 ; \
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0: mflr r0 ; \
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mtlr r1 ; \
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blr ;
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#define tlbentry(epn,sz,rpn,erpn,attr)\
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.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
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/**************************************************************************
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* TLB TABLE
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*
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* This table is used by the cpu boot code to setup the initial tlb
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* entries. Rather than make broad assumptions in the cpu source tree,
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* this table lets each board set things up however they like.
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*
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* Pointer to the table is returned in r1
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*
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*************************************************************************/
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.section .bootpg,"ax"
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.globl tlbtab
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tlbtab:
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tlbtab_start
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#if (CFG_LARGE_FLASH == 0xffc00000) /* if booting from large flash */
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/* large flash */
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tlbentry( 0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
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tlbentry( 0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
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tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
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tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
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tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
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tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
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#else /* else booting from small flash */
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tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
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tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
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tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
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tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
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tlbentry( 0xffa00000, SZ_1M, 0xffa00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
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tlbentry( 0xffb00000, SZ_1M, 0xffb00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
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#endif
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tlbentry( CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I )
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#if (CFG_SRAM_BASE != 0) /* if SRAM up high and SDRAM at zero */
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tlbentry( 0x00000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
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tlbentry( 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
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#elif (CFG_SMALL_FLASH == 0xff900000) /* else SRAM at 0 */
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tlbentry( 0x00000000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
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#elif (CFG_SMALL_FLASH == 0xfff00000)
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tlbentry( 0x00000000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
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#else
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#error DONT KNOW SRAM LOCATION
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#endif
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/* internal ram (l2 cache) */
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tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I )
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/* peripherals at f0000000 */
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tlbentry( CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I )
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/* PCI */
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#if (CONFIG_COMMANDS & CFG_CMD_PCI)
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tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I )
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tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I )
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#endif
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tlbtab_end
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