upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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30 lines
1.3 KiB
30 lines
1.3 KiB
17 years ago
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/* DO NOT EDIT THIS FILE
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* Automatically generated by generate-def-headers.xsl
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* DO NOT EDIT THIS FILE
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*/
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#ifndef __BFIN_DEF_ADSP_BF534_proc__
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#define __BFIN_DEF_ADSP_BF534_proc__
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#include "../mach-common/ADSP-EDN-core_def.h"
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#include "ADSP-EDN-BF534-extended_def.h"
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#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
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#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
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#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
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#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
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#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
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#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
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#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
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#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
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#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
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#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
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#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
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#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
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#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
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#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
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#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
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#endif /* __BFIN_DEF_ADSP_BF534_proc__ */
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