upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support
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u-boot/arch/x86/include/asm/cache.h

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/*
* Copyright (c) 2011 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __X86_CACHE_H__
#define __X86_CACHE_H__
/*
* If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise
* use 64-bytes, a safe default for x86.
*/
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN 64
#endif
static inline void wbinvd(void)
{
asm volatile ("wbinvd" : : : "memory");
}
static inline void invd(void)
{
asm volatile("invd" : : : "memory");
}
/* Enable caches and write buffer */
void enable_caches(void);
/* Disable caches and write buffer */
void disable_caches(void);
#endif /* __X86_CACHE_H__ */