upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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42 lines
1.4 KiB
42 lines
1.4 KiB
24 years ago
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#ifndef _MPC8260_IRQ_H
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#define _MPC8260_IRQ_H
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/****************************************************************************/
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/* most of this was ripped out of include/asm-ppc/irq.h from the Linux/PPC */
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/* source. There was no copyright information in the file. */
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/*
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* this is the # irq's for all ppc arch's (pmac/chrp/prep)
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* so it is the max of them all
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*
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* [let's just worry about 8260 for now - mjj]
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*/
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#define NR_IRQS 64
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/* The 8260 has an internal interrupt controller with a maximum of
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* 64 IRQs. We will use NR_IRQs from above since it is large enough.
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* Don't be confused by the 8260 documentation where they list an
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* "interrupt number" and "interrupt vector". We are only interested
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* in the interrupt vector. There are "reserved" holes where the
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* vector number increases, but the interrupt number in the table does not.
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* (Document errata updates have fixed this...make sure you have up to
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* date processor documentation -- Dan).
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*/
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#define NR_SIU_INTS 64
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/* There are many more than these, we will add them as we need them.
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*/
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#define SIU_INT_SMC1 ((uint)0x04)
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#define SIU_INT_SMC2 ((uint)0x05)
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#define SIU_INT_FCC1 ((uint)0x20)
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#define SIU_INT_FCC2 ((uint)0x21)
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#define SIU_INT_FCC3 ((uint)0x22)
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#define SIU_INT_SCC1 ((uint)0x28)
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#define SIU_INT_SCC2 ((uint)0x29)
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#define SIU_INT_SCC3 ((uint)0x2a)
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#define SIU_INT_SCC4 ((uint)0x2b)
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#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
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#endif /* _MPC8260_IRQ_H */
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