upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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157 lines
5.9 KiB
157 lines
5.9 KiB
20 years ago
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/*
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* (C) Copyright 2001
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* John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*************************************************************************
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* changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
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*
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************************************************************************/
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/*
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* mpsc.h - header file for MPSC in uart mode (console driver)
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*/
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#ifndef __MPSC_H__
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#define __MPSC_H__
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/* include actual Galileo defines */
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#include "../../Marvell/include/mv_gen_reg.h"
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/* driver related defines */
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int mpsc_init(int baud);
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void mpsc_sdma_init(void);
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void mpsc_init2(void);
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int galbrg_set_baudrate(int channel, int rate);
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int mpsc_putchar_early(char ch);
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char mpsc_getchar_debug(void);
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int mpsc_test_char_debug(void);
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int mpsc_test_char_sdma(void);
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extern int (*mpsc_putchar)(char ch);
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extern char (*mpsc_getchar)(void);
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extern int (*mpsc_test_char)(void);
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#define CHANNEL CONFIG_MPSC_PORT
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#define TX_DESC 5
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#define RX_DESC 20
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#define DESC_FIRST 0x00010000
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#define DESC_LAST 0x00020000
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#define DESC_OWNER_BIT 0x80000000
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#define TX_DEMAND 0x00800000
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#define TX_STOP 0x00010000
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#define RX_ENABLE 0x00000080
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#define SDMA_RX_ABORT (1 << 15)
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#define SDMA_TX_ABORT (1 << 31)
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#define MPSC_TX_ABORT (1 << 7)
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#define MPSC_RX_ABORT (1 << 23)
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#define MPSC_ENTER_HUNT (1 << 31)
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/* MPSC defines */
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#define GALMPSC_CONNECT 0x1
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#define GALMPSC_DISCONNECT 0x0
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#define GALMPSC_UART 0x1
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#define GALMPSC_STOP_BITS_1 0x0
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#define GALMPSC_STOP_BITS_2 0x1
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#define GALMPSC_CHAR_LENGTH_8 0x3
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#define GALMPSC_CHAR_LENGTH_7 0x2
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#define GALMPSC_PARITY_ODD 0x0
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#define GALMPSC_PARITY_EVEN 0x2
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#define GALMPSC_PARITY_MARK 0x3
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#define GALMPSC_PARITY_SPACE 0x1
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#define GALMPSC_PARITY_NONE -1
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#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */
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#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */
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#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */
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#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
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#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */
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#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */
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#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */
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#define GALMPSC_REG_GAP 0x1000
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#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */
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#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */
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#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */
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#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */
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#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */
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#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */
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#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */
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#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */
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#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */
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#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */
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#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */
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#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */
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#define GALSDMA_COMMAND_FIRST (1 << 16)
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#define GALSDMA_COMMAND_LAST (1 << 17)
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#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
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#define GALSDMA_COMMAND_AUTO (1 << 30)
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#define GALSDMA_COMMAND_OWNER (1 << 31)
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#define GALSDMA_RX 0
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#define GALSDMA_TX 1
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/* CHANNEL2 should be CHANNEL1, according to documentation,
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* but to work with the current GTREGS file...
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*/
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#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */
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#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */
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#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */
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#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */
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#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */
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#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */
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#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */
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#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */
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#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */
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#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */
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#define GALSDMA_REG_DIFF 0x2000
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/* WRONG in gt64260R.h */
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#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */
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#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */
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#define GALMPSC_0_INT_CAUSE 0xb804
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#define GALMPSC_0_INT_MASK 0xb884
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#define GALSDMA_MODE_UART 0
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#define GALSDMA_MODE_BISYNC 1
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#define GALSDMA_MODE_HDLC 2
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#define GALSDMA_MODE_TRANSPARENT 3
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#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */
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#define GALBRG_REG_GAP 0x0008
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#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */
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#endif /* __MPSC_H__ */
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