upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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214 lines
7.9 KiB
214 lines
7.9 KiB
17 years ago
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/*
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* LCD controller Memory Map
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __LCDC_H__
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#define __LCDC_H__
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/* LCD module registers */
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typedef struct lcd_ctrl {
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u32 ssar; /* 0x00 Screen Start Address Register */
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u32 sr; /* 0x04 LCD Size Register */
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u32 vpw; /* 0x08 Virtual Page Width Register */
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u32 cpr; /* 0x0C Cursor Position Register */
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u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */
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u32 ccmr; /* 0x14 Color Cursor Mapping Register */
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u32 pcr; /* 0x18 Panel Configuration Register */
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u32 hcr; /* 0x1C Horizontal Configuration Register */
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u32 vcr; /* 0x20 Vertical Configuration Register */
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u32 por; /* 0x24 Panning Offset Register */
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u32 scr; /* 0x28 Sharp Configuration Register */
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u32 pccr; /* 0x2C PWM Contrast Control Register */
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u32 dcr; /* 0x30 DMA Control Register */
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u32 rmcr; /* 0x34 Refresh Mode Control Register */
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u32 icr; /* 0x38 Refresh Mode Control Register */
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u32 ier; /* 0x3C Interrupt Enable Register */
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u32 isr; /* 0x40 Interrupt Status Register */
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u32 res[4];
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u32 gwsar; /* 0x50 Graphic Window Start Address Register */
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u32 gwsr; /* 0x54 Graphic Window Size Register */
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u32 gwvpw; /* 0x58 Graphic Window Virtual Page Width Register */
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u32 gwpor; /* 0x5C Graphic Window Panning Offset Register */
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u32 gwpr; /* 0x60 Graphic Window Position Register */
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u32 gwcr; /* 0x64 Graphic Window Control Register */
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u32 gwdcr; /* 0x68 Graphic Window DMA Control Register */
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} lcd_t;
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typedef struct lcdbg_ctrl {
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u32 bglut[255];
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} lcdbg_t;
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typedef struct lcdgw_ctrl {
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u32 gwlut[255];
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} lcdgw_t;
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/* Bit definitions and macros for LCDC_LSSAR */
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#define LCDC_SSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
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/* Bit definitions and macros for LCDC_LSR */
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#define LCDC_SR_XMAX(x) (((x)&0x0000003F)<<20)
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#define LCDC_SR_YMAX(x) ((x)&0x000003FF)
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/* Bit definitions and macros for LCDC_LVPWR */
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#define LCDC_VPWR_VPW(x) (((x)&0x000003FF)
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/* Bit definitions and macros for LCDC_LCPR */
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#define LCDC_CPR_CC(x) (((x)&0x00000003)<<30)
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#define LCDC_CPR_CC_AND (0xC0000000)
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#define LCDC_CPR_CC_XOR (0x80000000)
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#define LCDC_CPR_CC_OR (0x40000000)
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#define LCDC_CPR_CC_TRANSPARENT (0x00000000)
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#define LCDC_CPR_OP (0x10000000)
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#define LCDC_CPR_CXP(x) (((x)&0x000003FF)<<16)
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#define LCDC_CPR_CYP(x) ((x)&0x000003FF)
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/* Bit definitions and macros for LCDC_LCWHBR */
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#define LCDC_CWHBR_BK_EN (0x80000000)
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#define LCDC_CWHBR_CW(x) (((x)&0x0000001F)<<24)
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#define LCDC_CWHBR_CH(x) (((x)&0x0000001F)<<16)
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#define LCDC_CWHBR_BD(x) ((x)&0x000000FF)
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/* Bit definitions and macros for LCDC_LCCMR */
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#define LCDC_CCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
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#define LCDC_CCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
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#define LCDC_CCMR_CUR_COL_B(x) ((x)&0x0000003F)
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/* Bit definitions and macros for LCDC_LPCR */
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#define LCDC_PCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
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#define LCDC_PCR_MODE_TFT (0xC0000000)
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#define LCDC_PCR_MODE_CSTN (0x40000000)
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#define LCDC_PCR_MODE_MONOCHROME (0x00000000)
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#define LCDC_PCR_TFT (0x80000000)
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#define LCDC_PCR_COLOR (0x40000000)
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#define LCDC_PCR_PBSIZ(x) (((x)&0x00000003)<<28)
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#define LCDC_PCR_PBSIZ_8 (0x30000000)
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#define LCDC_PCR_PBSIZ_4 (0x20000000)
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#define LCDC_PCR_PBSIZ_2 (0x10000000)
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#define LCDC_PCR_PBSIZ_1 (0x00000000)
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#define LCDC_PCR_BPIX(x) (((x)&0x00000007)<<25)
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#define LCDC_PCR_BPIX_18bpp (0x0C000000)
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#define LCDC_PCR_BPIX_16bpp (0x0A000000)
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#define LCDC_PCR_BPIX_12bpp (0x08000000)
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#define LCDC_PCR_BPIX_8bpp (0x06000000)
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#define LCDC_PCR_BPIX_4bpp (0x04000000)
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#define LCDC_PCR_BPIX_2bpp (0x02000000)
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#define LCDC_PCR_BPIX_1bpp (0x00000000)
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#define LCDC_PCR_PIXPOL (0x01000000)
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#define LCDC_PCR_FLM (0x00800000)
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#define LCDC_PCR_LPPOL (0x00400000)
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#define LCDC_PCR_CLKPOL (0x00200000)
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#define LCDC_PCR_OEPOL (0x00100000)
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#define LCDC_PCR_SCLKIDLE (0x00080000)
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#define LCDC_PCR_ENDSEL (0x00040000)
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#define LCDC_PCR_SWAP_SEL (0x00020000)
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#define LCDC_PCR_REV_VS (0x00010000)
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#define LCDC_PCR_ACDSEL (0x00008000)
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#define LCDC_PCR_ACD(x) (((x)&0x0000007F)<<8)
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#define LCDC_PCR_SCLKSEL (0x00000080)
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#define LCDC_PCR_SHARP (0x00000040)
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#define LCDC_PCR_PCD(x) ((x)&0x0000003F)
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/* Bit definitions and macros for LCDC_LHCR */
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#define LCDC_HCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
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#define LCDC_HCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
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#define LCDC_HCR_H_WAIT_2(x) ((x)&0x000000FF)
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/* Bit definitions and macros for LCDC_LVCR */
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#define LCDC_VCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
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#define LCDC_VCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
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#define LCDC_VCR_V_WAIT_2(x) ((x)&0x000000FF)
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/* Bit definitions and macros for LCDC_SCR */
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#define LCDC_SCR_PS_R_DELAY(x) (((x)&0x0000003F) << 26)
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#define LCDC_SCR_CLS_R_DELAY(x) (((x)&0x000000FF) << 16)
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#define LCDC_SCR_RTG_DELAY(x) (((x)&0x0000000F) << 8)
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#define LCDC_SCR_GRAY2(x) (((x)&0x0000000F) << 4)
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#define LCDC_SCR_GRAY1(x) ((x)&&0x0000000F)
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/* Bit definitions and macros for LCDC_LPCCR */
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#define LCDC_PCCR_CLS_HI_WID(x) (((x)&0x000001FF)<<16)
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#define LCDC_PCCR_LDMSK (0x00008000)
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#define LCDC_PCCR_SCR(x) (((x)&0x00000003)<<9)
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#define LCDC_PCCR_SCR_LCDCLK (0x00000400)
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#define LCDC_PCCR_SCR_PIXCLK (0x00000200)
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#define LCDC_PCCR_SCR_LNPULSE (0x00000000)
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#define LCDC_PCCR_CC_EN (0x00000100)
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#define LCDC_PCCR_PW(x) ((x)&0x000000FF)
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/* Bit definitions and macros for LCDC_LDCR */
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#define LCDC_DCR_BURST (0x80000000)
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#define LCDC_DCR_HM(x) (((x)&0x0000001F)<<16)
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#define LCDC_DCR_TM(x) ((x)&0x0000001F)
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/* Bit definitions and macros for LCDC_LRMCR */
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#define LCDC_RMCR_SEL_REF (0x00000001)
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/* Bit definitions and macros for LCDC_LICR */
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#define LCDC_ICR_GW_INT_CON (0x00000010)
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#define LCDC_ICR_INTSYN (0x00000004)
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#define LCDC_ICR_INTCON (0x00000001)
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/* Bit definitions and macros for LCDC_LIER */
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#define LCDC_IER_GW_UDR (0x00000080)
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#define LCDC_IER_GW_ERR (0x00000040)
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#define LCDC_IER_GW_EOF (0x00000020)
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#define LCDC_IER_GW_BOF (0x00000010)
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#define LCDC_IER_UDR (0x00000008)
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#define LCDC_IER_ERR (0x00000004)
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#define LCDC_IER_EOF (0x00000002)
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#define LCDC_IER_BOF (0x00000001)
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/* Bit definitions and macros for LCDC_LGWSAR */
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#define LCDC_GWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
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/* Bit definitions and macros for LCDC_LGWSR */
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#define LCDC_GWSR_GWW(x) (((x)&0x0000003F)<<20)
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#define LCDC_GWSR_GWH(x) ((x)&0x000003FF)
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/* Bit definitions and macros for LCDC_LGWVPWR */
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#define LCDC_GWVPWR_GWVPW(x) ((x)&0x000003FF)
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/* Bit definitions and macros for LCDC_LGWPOR */
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#define LCDC_GWPOR_GWPO(x) ((x)&0x0000001F)
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/* Bit definitions and macros for LCDC_LGWPR */
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#define LCDC_GWPR_GWXP(x) (((x)&0x000003FF)<<16)
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#define LCDC_GWPR_GWYP(x) ((x)&0x000003FF)
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/* Bit definitions and macros for LCDC_LGWCR */
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#define LCDC_GWCR_GWAV(x) (((x)&0x000000FF)<<24)
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#define LCDC_GWCR_GWCKE (0x00800000)
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#define LCDC_LGWCR_GWE (0x00400000)
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#define LCDC_LGWCR_GW_RVS (0x00200000)
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#define LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
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#define LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
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#define LCDC_LGWCR_GWCKB(x) ((x)&0x0000003F)
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/* Bit definitions and macros for LCDC_LGWDCR */
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#define LCDC_LGWDCR_GWBT (0x80000000)
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#define LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
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#define LCDC_LGWDCR_GWTM(x) ((x)&0x0000001F)
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#endif /* __LCDC_H__ */
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