upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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63 lines
2.0 KiB
63 lines
2.0 KiB
13 years ago
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/*
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* (C) Copyright 2011
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* Linaro
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* Linus Walleij <linus.walleij@linaro.org>
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* Register definitions for the External Bus Interface (EBI)
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* found in the ARM Integrator AP and CP reference designs
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ARM_EBI_H
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#define __ARM_EBI_H
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#define EBI_BASE 0x12000000
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#define EBI_CSR0_REG 0x00 /* CS0 = Boot ROM */
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#define EBI_CSR1_REG 0x04 /* CS1 = Flash */
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#define EBI_CSR2_REG 0x08 /* CS2 = SSRAM */
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#define EBI_CSR3_REG 0x0C /* CS3 = Expansion memory */
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/*
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* The four upper bits are the waitstates for each chip select
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* 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles
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*/
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#define EBI_CSR_WAIT_MASK 0xF0
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/* Whether memory is synchronous or asynchronous */
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#define EBI_CSR_SYNC_MASK 0xF7
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#define EBI_CSR_ASYNC 0x00
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#define EBI_CSR_SYNC 0x08
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/* Whether memory is write enabled or not */
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#define EBI_CSR_WREN_MASK 0xFB
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#define EBI_CSR_WREN_DISABLE 0x00
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#define EBI_CSR_WREN_ENABLE 0x04
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/* Memory bit width for each chip select */
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#define EBI_CSR_MEMSIZE_MASK 0xFC
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#define EBI_CSR_MEMSIZE_8BIT 0x00
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#define EBI_CSR_MEMSIZE_16BIT 0x01
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#define EBI_CSR_MEMSIZE_32BIT 0x02
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/*
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* The lock register need to be written with 0xa05f before anything in the
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* EBI can be changed.
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*/
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#define EBI_LOCK_REG 0x20
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#define EBI_UNLOCK_MAGIC 0xA05F
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#endif
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