u-boot/board/freescale/common/ics307_clk.h

/*
 * Copyright 2010-2011 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __ICS_CLK_H_
#define __ICS_CLK_H_	1

#ifndef __ASSEMBLY__

extern unsigned long get_board_sys_clk(void);
extern unsigned long get_board_ddr_clk(void);
extern unsigned long ics307_sysclk_calculator(unsigned long out_freq);
#endif

#endif	/* __ICS_CLK_H_ */
Move ICS CLK chip frequency calculation code into a common board library We have several boards that use the same ICS307 CLK chip to drive the System clock and DDR clock. Move the code into a common location so we share it. Convert the P2020DS board as the first to use the new common ICS307 code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Timur Tabi <timur@freescale.com> 15 years ago			`/*`
powerpc/mpc85xx: Set SYSCLK to the required frequency For ICS307-02, there is one general expression to generate SYSCLK: CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) If we want the required frequency for SYSCLK, we must find one solution to generate this frequency, this solution includes VDW, RDW and OD. For OD, there are only eight option value: 10, 2, 8, 4, 5, 7, 3, 6. For RDW, the range is 1 to 127. For VDW, the range is 4 to 511. First, we use one OD, RDW and required SYSCLK to calculate the VDW, if VDW is in it's range, we will calculate the CLK1Frequency with the OD, RDW and VDW calculated, and we will check this percent (CLK1Frequency / required SYSCLK), and the precision is 1/1000. if the percent is less than 1/1000, we think the CLK1Frequency is we want. Otherwise, We will continue to calculate it with the next OD and RDW. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 13 years ago			`* Copyright 2010-2011 Freescale Semiconductor, Inc.`
Move ICS CLK chip frequency calculation code into a common board library We have several boards that use the same ICS307 CLK chip to drive the System clock and DDR clock. Move the code into a common location so we share it. Convert the P2020DS board as the first to use the new common ICS307 code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Timur Tabi <timur@freescale.com> 15 years ago			`*`
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> 12 years ago			`* SPDX-License-Identifier: GPL-2.0+`
Move ICS CLK chip frequency calculation code into a common board library We have several boards that use the same ICS307 CLK chip to drive the System clock and DDR clock. Move the code into a common location so we share it. Convert the P2020DS board as the first to use the new common ICS307 code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Timur Tabi <timur@freescale.com> 15 years ago			`*/`
			`#ifndef __ICS_CLK_H_`
			`#define __ICS_CLK_H_ 1`

			`#ifndef __ASSEMBLY__`
powerpc/mpc85xx: Set SYSCLK to the required frequency For ICS307-02, there is one general expression to generate SYSCLK: CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) If we want the required frequency for SYSCLK, we must find one solution to generate this frequency, this solution includes VDW, RDW and OD. For OD, there are only eight option value: 10, 2, 8, 4, 5, 7, 3, 6. For RDW, the range is 1 to 127. For VDW, the range is 4 to 511. First, we use one OD, RDW and required SYSCLK to calculate the VDW, if VDW is in it's range, we will calculate the CLK1Frequency with the OD, RDW and VDW calculated, and we will check this percent (CLK1Frequency / required SYSCLK), and the precision is 1/1000. if the percent is less than 1/1000, we think the CLK1Frequency is we want. Otherwise, We will continue to calculate it with the next OD and RDW. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 13 years ago
Move ICS CLK chip frequency calculation code into a common board library We have several boards that use the same ICS307 CLK chip to drive the System clock and DDR clock. Move the code into a common location so we share it. Convert the P2020DS board as the first to use the new common ICS307 code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Timur Tabi <timur@freescale.com> 15 years ago			`extern unsigned long get_board_sys_clk(void);`
			`extern unsigned long get_board_ddr_clk(void);`
powerpc/mpc85xx: Set SYSCLK to the required frequency For ICS307-02, there is one general expression to generate SYSCLK: CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) If we want the required frequency for SYSCLK, we must find one solution to generate this frequency, this solution includes VDW, RDW and OD. For OD, there are only eight option value: 10, 2, 8, 4, 5, 7, 3, 6. For RDW, the range is 1 to 127. For VDW, the range is 4 to 511. First, we use one OD, RDW and required SYSCLK to calculate the VDW, if VDW is in it's range, we will calculate the CLK1Frequency with the OD, RDW and VDW calculated, and we will check this percent (CLK1Frequency / required SYSCLK), and the precision is 1/1000. if the percent is less than 1/1000, we think the CLK1Frequency is we want. Otherwise, We will continue to calculate it with the next OD and RDW. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 13 years ago			`extern unsigned long ics307_sysclk_calculator(unsigned long out_freq);`
Move ICS CLK chip frequency calculation code into a common board library We have several boards that use the same ICS307 CLK chip to drive the System clock and DDR clock. Move the code into a common location so we share it. Convert the P2020DS board as the first to use the new common ICS307 code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Timur Tabi <timur@freescale.com> 15 years ago			`#endif`

			`#endif /* __ICS_CLK_H_ */`