upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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109 lines
2.6 KiB
109 lines
2.6 KiB
16 years ago
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <usb.h>
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#include "ehci.h"
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#include "ehci-core.h"
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#include <asm/arch/kirkwood.h>
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#define rdl(off) readl(KW_USB20_BASE + (off))
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#define wrl(off, val) writel((val), KW_USB20_BASE + (off))
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#define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
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#define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
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#define USB_TARGET_DRAM 0x0
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/*
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* USB 2.0 Bridge Address Decoding registers setup
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*/
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static void usb_brg_adrdec_setup(void)
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{
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int i;
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u32 size, attrib;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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/* Enable DRAM bank */
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switch (i) {
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case 0:
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attrib = KWCPU_ATTR_DRAM_CS0;
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break;
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case 1:
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attrib = KWCPU_ATTR_DRAM_CS1;
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break;
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case 2:
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attrib = KWCPU_ATTR_DRAM_CS2;
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break;
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case 3:
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attrib = KWCPU_ATTR_DRAM_CS3;
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break;
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default:
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/* invalide bank, disable access */
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attrib = 0;
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break;
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}
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size = kw_sdram_bs(i);
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if ((size) && (attrib))
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wrl(USB_WINDOW_CTRL(i),
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KWCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
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attrib, KWCPU_WIN_ENABLE));
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else
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wrl(USB_WINDOW_CTRL(i), KWCPU_WIN_DISABLE);
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wrl(USB_WINDOW_BASE(i), kw_sdram_bar(i));
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}
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}
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/*
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* Create the appropriate control structures to manage
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* a new EHCI host controller.
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*/
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int ehci_hcd_init(void)
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{
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usb_brg_adrdec_setup();
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hccr = (struct ehci_hccr *)(KW_USB20_BASE + 0x100);
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hcor = (struct ehci_hcor *)((uint32_t) hccr
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+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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debug("Kirkwood-ehci: init hccr %x and hcor %x hc_length %d\n",
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(uint32_t)hccr, (uint32_t)hcor,
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(uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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return 0;
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}
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/*
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* Destroy the appropriate control structures corresponding
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* the the EHCI host controller.
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*/
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int ehci_hcd_stop(void)
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{
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return 0;
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}
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