upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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67 lines
1.4 KiB
67 lines
1.4 KiB
12 years ago
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/*
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* watchdog.c - driver for i.mx on-chip watchdog
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <watchdog.h>
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#include <asm/arch/imx-regs.h>
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struct watchdog_regs {
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u16 wcr; /* Control */
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u16 wsr; /* Service */
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u16 wrsr; /* Reset Status */
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};
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#define WCR_WDZST 0x01
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#define WCR_WDBG 0x02
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#define WCR_WDE 0x04 /* WDOG enable */
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#define WCR_WDT 0x08
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#define WCR_WDW 0x80
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#define SET_WCR_WT(x) (x << 8)
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#ifdef CONFIG_IMX_WATCHDOG
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void hw_watchdog_reset(void)
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{
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struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
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writew(0x5555, &wdog->wsr);
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writew(0xaaaa, &wdog->wsr);
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}
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void hw_watchdog_init(void)
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{
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struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
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u16 timeout;
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/*
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* The timer watchdog can be set between
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* 0.5 and 128 Seconds. If not defined
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* in configuration file, sets 128 Seconds
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*/
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#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
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#define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
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#endif
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timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
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writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT |
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WCR_WDW | SET_WCR_WT(timeout), &wdog->wcr);
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hw_watchdog_reset();
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}
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#endif
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void reset_cpu(ulong addr)
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{
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struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
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writew(WCR_WDE, &wdog->wcr);
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writew(0x5555, &wdog->wsr);
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writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */
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while (1) {
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/*
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* spin for .5 seconds before reset
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*/
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}
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}
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