upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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104 lines
2.5 KiB
104 lines
2.5 KiB
17 years ago
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include "ddr.h"
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unsigned int fsl_ddr_get_mem_data_rate(void);
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/*
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* Round mclk_ps to nearest 10 ps in memory controller code.
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*
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* If an imprecise data rate is too high due to rounding error
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* propagation, compute a suitably rounded mclk_ps to compute
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* a working memory controller configuration.
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*/
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unsigned int get_memory_clk_period_ps(void)
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{
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unsigned int mclk_ps;
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mclk_ps = 2000000000000ULL / fsl_ddr_get_mem_data_rate();
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/* round to nearest 10 ps */
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return 10 * ((mclk_ps + 5) / 10);
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}
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/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
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unsigned int picos_to_mclk(unsigned int picos)
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{
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const unsigned long long ULL_2e12 = 2000000000000ULL;
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const unsigned long long ULL_8Fs = 0xFFFFFFFFULL;
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unsigned long long clks;
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unsigned long long clks_temp;
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if (!picos)
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return 0;
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clks = fsl_ddr_get_mem_data_rate() * (unsigned long long) picos;
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clks_temp = clks;
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clks = clks / ULL_2e12;
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if (clks_temp % ULL_2e12) {
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clks++;
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}
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if (clks > ULL_8Fs) {
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clks = ULL_8Fs;
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}
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return (unsigned int) clks;
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}
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unsigned int mclk_to_picos(unsigned int mclk)
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{
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return get_memory_clk_period_ps() * mclk;
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}
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void
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__fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
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unsigned int memctl_interleaved,
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unsigned int ctrl_num)
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{
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/*
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* If no DIMMs on this controller, do not proceed any further.
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*/
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if (!memctl_common_params->ndimms_present) {
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return;
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}
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if (ctrl_num == 0) {
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/*
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* Set up LAW for DDR controller 1 space.
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*/
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unsigned int lawbar1_target_id = memctl_interleaved
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? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1;
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if (set_ddr_laws(memctl_common_params->base_address,
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memctl_common_params->total_mem,
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lawbar1_target_id) < 0) {
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printf("ERROR\n");
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return ;
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}
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} else if (ctrl_num == 1) {
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if (set_ddr_laws(memctl_common_params->base_address,
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memctl_common_params->total_mem,
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LAW_TRGT_IF_DDR_2) < 0) {
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printf("ERROR\n");
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return ;
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}
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} else {
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printf("unexpected controller number %u in %s\n",
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ctrl_num, __FUNCTION__);
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}
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}
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__attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
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fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
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unsigned int memctl_interleaved,
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unsigned int ctrl_num);
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