upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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129 lines
1.9 KiB
129 lines
1.9 KiB
18 years ago
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#define ASSEMBLY
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#include <asm/linkage.h>
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#include <config.h>
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#include <asm/blackfin.h>
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.text
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.align 2
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ENTRY(_blackfin_icache_flush_range)
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R2 = -32;
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R2 = R0 & R2;
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P0 = R2;
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P1 = R1;
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CSYNC;
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1:
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IFLUSH[P0++];
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CC = P0 < P1(iu);
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IF CC JUMP 1b(bp);
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IFLUSH[P0];
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SSYNC;
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RTS;
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ENTRY(_blackfin_dcache_flush_range)
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R2 = -32;
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R2 = R0 & R2;
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P0 = R2;
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P1 = R1;
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CSYNC;
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1:
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FLUSH[P0++];
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CC = P0 < P1(iu);
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IF CC JUMP 1b(bp);
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FLUSH[P0];
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SSYNC;
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RTS;
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ENTRY(_icache_invalidate)
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ENTRY(_invalidate_entire_icache)
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[--SP] = (R7:5);
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P0.L = (IMEM_CONTROL & 0xFFFF);
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P0.H = (IMEM_CONTROL >> 16);
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R7 =[P0];
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/*
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* Clear the IMC bit , All valid bits in the instruction
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* cache are set to the invalid state
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*/
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BITCLR(R7, IMC_P);
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CLI R6;
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/* SSYNC required before invalidating cache. */
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SSYNC;
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.align 8;
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[P0] = R7;
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SSYNC;
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STI R6;
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/* Configures the instruction cache agian */
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R6 = (IMC | ENICPLB);
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R7 = R7 | R6;
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CLI R6;
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SSYNC;
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.align 8;
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[P0] = R7;
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SSYNC;
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STI R6;
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(R7:5) =[SP++];
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RTS;
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/*
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* Invalidate the Entire Data cache by
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* clearing DMC[1:0] bits
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*/
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ENTRY(_invalidate_entire_dcache)
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ENTRY(_dcache_invalidate)
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[--SP] = (R7:6);
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P0.L = (DMEM_CONTROL & 0xFFFF);
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P0.H = (DMEM_CONTROL >> 16);
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R7 =[P0];
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/*
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* Clear the DMC[1:0] bits, All valid bits in the data
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* cache are set to the invalid state
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*/
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BITCLR(R7, DMC0_P);
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BITCLR(R7, DMC1_P);
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CLI R6;
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SSYNC;
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.align 8;
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[P0] = R7;
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SSYNC;
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STI R6;
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/* Configures the data cache again */
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R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
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R7 = R7 | R6;
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CLI R6;
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SSYNC;
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.align 8;
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[P0] = R7;
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SSYNC;
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STI R6;
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(R7:6) =[SP++];
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RTS;
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ENTRY(_blackfin_dcache_invalidate_range)
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R2 = -32;
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R2 = R0 & R2;
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P0 = R2;
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P1 = R1;
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CSYNC;
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1:
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FLUSHINV[P0++];
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CC = P0 < P1(iu);
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IF CC JUMP 1b(bp);
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/*
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* If the data crosses a cache line, then we'll be pointing to
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* the last cache line, but won't have flushed/invalidated it yet, so do
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* one more.
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*/
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FLUSHINV[P0];
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SSYNC;
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RTS;
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