upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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499 lines
13 KiB
499 lines
13 KiB
23 years ago
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
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*/
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/*
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* Minimal serial functions needed to use one of the SCC ports
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* as serial console interface.
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*/
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#include <common.h>
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#include <mpc8260.h>
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#include <asm/cpm_8260.h>
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#if defined(CONFIG_CONS_ON_SCC)
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#if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */
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#define SCC_INDEX 0
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#define PROFF_SCC PROFF_SCC1
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#define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\
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CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
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#define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
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#define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE
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#define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK
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#elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */
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#define SCC_INDEX 1
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#define PROFF_SCC PROFF_SCC2
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#define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\
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CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
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#define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
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#define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE
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#define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK
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#elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */
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#define SCC_INDEX 2
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#define PROFF_SCC PROFF_SCC3
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#define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\
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CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
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#define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
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#define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE
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#define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK
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#elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */
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#define SCC_INDEX 3
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#define PROFF_SCC PROFF_SCC4
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#define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\
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CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
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#define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
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#define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE
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#define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK
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#else
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#error "console not correctly defined"
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#endif
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int serial_init (void)
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{
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volatile immap_t *im = (immap_t *)CFG_IMMR;
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volatile scc_t *sp;
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volatile scc_uart_t *up;
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volatile cbd_t *tbdf, *rbdf;
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volatile cpm8260_t *cp = &(im->im_cpm);
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uint dpaddr;
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/* initialize pointers to SCC */
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sp = (scc_t *) &(im->im_scc[SCC_INDEX]);
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up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
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/* Disable transmitter/receiver.
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*/
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sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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/* put the SCC channel into NMSI (non multiplexd serial interface)
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* mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
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*/
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im->im_cpmux.cmx_scr = (im->im_cpmux.cmx_scr&~CMXSCR_MASK)|CMXSCR_VALUE;
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/* Set up the baud rate generator.
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*/
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serial_setbrg ();
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/* Allocate space for two buffer descriptors in the DP ram.
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* damm: allocating space after the two buffers for rx/tx data
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*/
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dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
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/* Set the physical address of the host memory buffers in
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* the buffer descriptors.
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*/
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rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
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rbdf->cbd_bufaddr = (uint) (rbdf+2);
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rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
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tbdf = rbdf + 1;
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tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
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tbdf->cbd_sc = BD_SC_WRAP;
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/* Set up the uart parameters in the parameter ram.
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*/
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up->scc_genscc.scc_rbase = dpaddr;
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up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
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up->scc_genscc.scc_rfcr = CPMFCR_EB;
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up->scc_genscc.scc_tfcr = CPMFCR_EB;
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up->scc_genscc.scc_mrblr = 1;
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up->scc_maxidl = 0;
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up->scc_brkcr = 1;
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up->scc_parec = 0;
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up->scc_frmec = 0;
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up->scc_nosec = 0;
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up->scc_brkec = 0;
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up->scc_uaddr1 = 0;
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up->scc_uaddr2 = 0;
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up->scc_toseq = 0;
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up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
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up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
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up->scc_rccm = 0xc0ff;
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/* Mask all interrupts and remove anything pending.
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*/
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sp->scc_sccm = 0;
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sp->scc_scce = 0xffff;
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/* Set 8 bit FIFO, 16 bit oversampling and UART mode.
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*/
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sp->scc_gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */
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sp->scc_gsmrl = \
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SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;
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/* Set CTS flow control, 1 stop bit, 8 bit character length,
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* normal async UART mode, no parity
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*/
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sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL;
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/* execute the "Init Rx and Tx params" CP command.
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*/
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while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
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;
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cp->cp_cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
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0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
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while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
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;
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/* Enable transmitter/receiver.
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*/
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sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;
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return (0);
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}
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void
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serial_setbrg (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_CONS_USE_EXTC)
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m8260_cpm_extcbrg(SCC_INDEX, gd->baudrate,
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CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
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#else
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m8260_cpm_setbrg(SCC_INDEX, gd->baudrate);
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#endif
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}
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void
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serial_putc(const char c)
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{
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volatile scc_uart_t *up;
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volatile cbd_t *tbdf;
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volatile immap_t *im;
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if (c == '\n')
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serial_putc ('\r');
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im = (immap_t *)CFG_IMMR;
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up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
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tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];
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/* Wait for last character to go.
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*/
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while (tbdf->cbd_sc & BD_SC_READY)
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;
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/* Load the character into the transmit buffer.
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*/
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*(volatile char *)tbdf->cbd_bufaddr = c;
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tbdf->cbd_datlen = 1;
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tbdf->cbd_sc |= BD_SC_READY;
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}
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void
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serial_puts (const char *s)
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{
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while (*s) {
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serial_putc (*s++);
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}
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}
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int
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serial_getc(void)
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{
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volatile cbd_t *rbdf;
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volatile scc_uart_t *up;
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volatile immap_t *im;
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unsigned char c;
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im = (immap_t *)CFG_IMMR;
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up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
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rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
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/* Wait for character to show up.
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*/
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while (rbdf->cbd_sc & BD_SC_EMPTY)
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;
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/* Grab the char and clear the buffer again.
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*/
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c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
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rbdf->cbd_sc |= BD_SC_EMPTY;
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return (c);
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}
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int
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serial_tstc()
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{
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volatile cbd_t *rbdf;
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volatile scc_uart_t *up;
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volatile immap_t *im;
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im = (immap_t *)CFG_IMMR;
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up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
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rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
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return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
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}
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#endif /* CONFIG_CONS_ON_SCC */
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#if defined(CONFIG_KGDB_ON_SCC)
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#if defined(CONFIG_CONS_ON_SCC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
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#error Whoops! serial console and kgdb are on the same scc serial port
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#endif
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#if CONFIG_KGDB_INDEX == 1 /* KGDB Port on SCC1 */
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#define KGDB_SCC_INDEX 0
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#define KGDB_PROFF_SCC PROFF_SCC1
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#define KGDB_CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\
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CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
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#define KGDB_CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
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#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE
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#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK
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#elif CONFIG_KGDB_INDEX == 2 /* KGDB Port on SCC2 */
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#define KGDB_SCC_INDEX 1
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#define KGDB_PROFF_SCC PROFF_SCC2
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#define KGDB_CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\
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CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
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#define KGDB_CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
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#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE
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#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK
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#elif CONFIG_KGDB_INDEX == 3 /* KGDB Port on SCC3 */
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#define KGDB_SCC_INDEX 2
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#define KGDB_PROFF_SCC PROFF_SCC3
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#define KGDB_CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\
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CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
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#define KGDB_CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
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#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE
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#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK
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#elif CONFIG_KGDB_INDEX == 4 /* KGDB Port on SCC4 */
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#define KGDB_SCC_INDEX 3
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#define KGDB_PROFF_SCC PROFF_SCC4
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#define KGDB_CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\
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CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
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#define KGDB_CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
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#define KGDB_CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE
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#define KGDB_CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK
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#else
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#error "kgdb serial port not correctly defined"
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#endif
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void
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kgdb_serial_init (void)
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{
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volatile immap_t *im = (immap_t *)CFG_IMMR;
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volatile scc_t *sp;
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volatile scc_uart_t *up;
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volatile cbd_t *tbdf, *rbdf;
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volatile cpm8260_t *cp = &(im->im_cpm);
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uint dpaddr, speed = CONFIG_KGDB_BAUDRATE;
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char *s, *e;
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||
|
|
|
||
|
|
if ((s = getenv("kgdbrate")) != NULL && *s != '\0') {
|
||
|
|
ulong rate = simple_strtoul(s, &e, 10);
|
||
|
|
if (e > s && *e == '\0')
|
||
|
|
speed = rate;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* initialize pointers to SCC */
|
||
|
|
|
||
|
|
sp = (scc_t *) &(im->im_scc[KGDB_SCC_INDEX]);
|
||
|
|
up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
|
||
|
|
|
||
|
|
/* Disable transmitter/receiver.
|
||
|
|
*/
|
||
|
|
sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
||
|
|
|
||
|
|
/* put the SCC channel into NMSI (non multiplexd serial interface)
|
||
|
|
* mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
|
||
|
|
*/
|
||
|
|
im->im_cpmux.cmx_scr = \
|
||
|
|
(im->im_cpmux.cmx_scr & ~KGDB_CMXSCR_MASK) | KGDB_CMXSCR_VALUE;
|
||
|
|
|
||
|
|
/* Set up the baud rate generator.
|
||
|
|
*/
|
||
|
|
#if defined(CONFIG_KGDB_USE_EXTC)
|
||
|
|
m8260_cpm_extcbrg(KGDB_SCC_INDEX, speed,
|
||
|
|
CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
|
||
|
|
#else
|
||
|
|
m8260_cpm_setbrg(KGDB_SCC_INDEX, speed);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Allocate space for two buffer descriptors in the DP ram.
|
||
|
|
* damm: allocating space after the two buffers for rx/tx data
|
||
|
|
*/
|
||
|
|
|
||
|
|
dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
|
||
|
|
|
||
|
|
/* Set the physical address of the host memory buffers in
|
||
|
|
* the buffer descriptors.
|
||
|
|
*/
|
||
|
|
rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
|
||
|
|
rbdf->cbd_bufaddr = (uint) (rbdf+2);
|
||
|
|
rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
|
||
|
|
tbdf = rbdf + 1;
|
||
|
|
tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
|
||
|
|
tbdf->cbd_sc = BD_SC_WRAP;
|
||
|
|
|
||
|
|
/* Set up the uart parameters in the parameter ram.
|
||
|
|
*/
|
||
|
|
up->scc_genscc.scc_rbase = dpaddr;
|
||
|
|
up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
|
||
|
|
up->scc_genscc.scc_rfcr = CPMFCR_EB;
|
||
|
|
up->scc_genscc.scc_tfcr = CPMFCR_EB;
|
||
|
|
up->scc_genscc.scc_mrblr = 1;
|
||
|
|
up->scc_maxidl = 0;
|
||
|
|
up->scc_brkcr = 1;
|
||
|
|
up->scc_parec = 0;
|
||
|
|
up->scc_frmec = 0;
|
||
|
|
up->scc_nosec = 0;
|
||
|
|
up->scc_brkec = 0;
|
||
|
|
up->scc_uaddr1 = 0;
|
||
|
|
up->scc_uaddr2 = 0;
|
||
|
|
up->scc_toseq = 0;
|
||
|
|
up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
|
||
|
|
up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
|
||
|
|
up->scc_rccm = 0xc0ff;
|
||
|
|
|
||
|
|
/* Mask all interrupts and remove anything pending.
|
||
|
|
*/
|
||
|
|
sp->scc_sccm = 0;
|
||
|
|
sp->scc_scce = 0xffff;
|
||
|
|
|
||
|
|
/* Set 8 bit FIFO, 16 bit oversampling and UART mode.
|
||
|
|
*/
|
||
|
|
sp->scc_gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */
|
||
|
|
sp->scc_gsmrl = \
|
||
|
|
SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;
|
||
|
|
|
||
|
|
/* Set CTS flow control, 1 stop bit, 8 bit character length,
|
||
|
|
* normal async UART mode, no parity
|
||
|
|
*/
|
||
|
|
sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL;
|
||
|
|
|
||
|
|
/* execute the "Init Rx and Tx params" CP command.
|
||
|
|
*/
|
||
|
|
|
||
|
|
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
|
||
|
|
;
|
||
|
|
|
||
|
|
cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SCC_PAGE, KGDB_CPM_CR_SCC_SBLOCK,
|
||
|
|
0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
|
||
|
|
|
||
|
|
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
|
||
|
|
;
|
||
|
|
|
||
|
|
/* Enable transmitter/receiver.
|
||
|
|
*/
|
||
|
|
sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;
|
||
|
|
|
||
|
|
printf("SCC%d at %dbps ", CONFIG_KGDB_INDEX, speed);
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
putDebugChar(const char c)
|
||
|
|
{
|
||
|
|
volatile scc_uart_t *up;
|
||
|
|
volatile cbd_t *tbdf;
|
||
|
|
volatile immap_t *im;
|
||
|
|
|
||
|
|
if (c == '\n')
|
||
|
|
putDebugChar ('\r');
|
||
|
|
|
||
|
|
im = (immap_t *)CFG_IMMR;
|
||
|
|
up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
|
||
|
|
tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];
|
||
|
|
|
||
|
|
/* Wait for last character to go.
|
||
|
|
*/
|
||
|
|
while (tbdf->cbd_sc & BD_SC_READY)
|
||
|
|
;
|
||
|
|
|
||
|
|
/* Load the character into the transmit buffer.
|
||
|
|
*/
|
||
|
|
*(volatile char *)tbdf->cbd_bufaddr = c;
|
||
|
|
tbdf->cbd_datlen = 1;
|
||
|
|
tbdf->cbd_sc |= BD_SC_READY;
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
putDebugStr (const char *s)
|
||
|
|
{
|
||
|
|
while (*s) {
|
||
|
|
putDebugChar (*s++);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
int
|
||
|
|
getDebugChar(void)
|
||
|
|
{
|
||
|
|
volatile cbd_t *rbdf;
|
||
|
|
volatile scc_uart_t *up;
|
||
|
|
volatile immap_t *im;
|
||
|
|
unsigned char c;
|
||
|
|
|
||
|
|
im = (immap_t *)CFG_IMMR;
|
||
|
|
up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
|
||
|
|
rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
|
||
|
|
|
||
|
|
/* Wait for character to show up.
|
||
|
|
*/
|
||
|
|
while (rbdf->cbd_sc & BD_SC_EMPTY)
|
||
|
|
;
|
||
|
|
|
||
|
|
/* Grab the char and clear the buffer again.
|
||
|
|
*/
|
||
|
|
c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
|
||
|
|
rbdf->cbd_sc |= BD_SC_EMPTY;
|
||
|
|
|
||
|
|
return (c);
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
kgdb_interruptible(int yes)
|
||
|
|
{
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* CONFIG_KGDB_ON_SCC */
|