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// SPDX-License-Identifier: GPL-2.0+
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/*
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* dts file for Xilinx ZynqMP ZCU111
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*
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* (C) Copyright 2017 - 2018, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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model = "ZynqMP ZCU111 RevA";
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compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem3;
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gpio0 = &gpio;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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mmc0 = &sdhci1;
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rtc0 = &rtc;
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serial0 = &uart0;
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serial1 = &dcc;
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spi0 = &qspi;
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usb0 = &usb0;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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/* Another 4GB connected to PL */
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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sw19 {
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label = "sw19";
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gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
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linux,code = <KEY_DOWN>;
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gpio-key,wakeup;
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autorepeat;
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};
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};
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leds {
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compatible = "gpio-leds";
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heartbeat_led {
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label = "heartbeat";
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gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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};
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&dcc {
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status = "okay";
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};
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&fpd_dma_chan1 {
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status = "okay";
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};
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&fpd_dma_chan2 {
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status = "okay";
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};
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&fpd_dma_chan3 {
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status = "okay";
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};
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&fpd_dma_chan4 {
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status = "okay";
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};
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&fpd_dma_chan5 {
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status = "okay";
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};
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&fpd_dma_chan6 {
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status = "okay";
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};
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&fpd_dma_chan7 {
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status = "okay";
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};
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&fpd_dma_chan8 {
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status = "okay";
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};
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&gem3 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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phy0: phy@c {
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reg = <0xc>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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};
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};
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&gpio {
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status = "okay";
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};
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&gpu {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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tca6416_u22: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller; /* interrupt not connected */
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#gpio-cells = <2>;
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/*
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* IRQ not connected
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* Lines:
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* 0 - MAX6643_OT_B
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* 1 - MAX6643_FANFAIL_B
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* 2 - MIO26_PMU_INPUT_LS
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* 4 - SFP_SI5382_INT_ALM
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* 5 - IIC_MUX_RESET_B
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* 6 - GEM3_EXP_RESET_B
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* 10 - FMCP_HSPC_PRSNT_M2C_B
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* 11 - CLK_SPI_MUX_SEL0
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* 12 - CLK_SPI_MUX_SEL1
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* 16 - IRPS5401_ALERT_B
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* 17 - INA226_PMBUS_ALERT
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* 3, 7, 13-15 - not connected
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*/
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};
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i2c-mux@75 { /* u23 */
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compatible = "nxp,pca9544";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x75>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/* PS_PMBUS */
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/* PMBUS_ALERT done via pca9544 */
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ina226@40 { /* u67 */
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compatible = "ti,ina226";
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reg = <0x40>;
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shunt-resistor = <2000>;
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};
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ina226@41 { /* u59 */
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compatible = "ti,ina226";
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reg = <0x41>;
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shunt-resistor = <5000>;
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};
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ina226@42 { /* u61 */
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compatible = "ti,ina226";
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reg = <0x42>;
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shunt-resistor = <5000>;
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};
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ina226@43 { /* u60 */
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compatible = "ti,ina226";
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reg = <0x43>;
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shunt-resistor = <5000>;
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};
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ina226@45 { /* u64 */
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compatible = "ti,ina226";
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reg = <0x45>;
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shunt-resistor = <5000>;
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};
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ina226@46 { /* u69 */
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compatible = "ti,ina226";
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reg = <0x46>;
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shunt-resistor = <2000>;
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};
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ina226@47 { /* u66 */
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compatible = "ti,ina226";
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reg = <0x47>;
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shunt-resistor = <5000>;
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};
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ina226@48 { /* u65 */
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compatible = "ti,ina226";
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reg = <0x48>;
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shunt-resistor = <5000>;
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};
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ina226@49 { /* u63 */
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compatible = "ti,ina226";
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reg = <0x49>;
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shunt-resistor = <5000>;
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};
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ina226@4a { /* u3 */
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compatible = "ti,ina226";
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reg = <0x4a>;
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shunt-resistor = <5000>;
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};
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ina226@4b { /* u71 */
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compatible = "ti,ina226";
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reg = <0x4b>;
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shunt-resistor = <5000>;
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};
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ina226@4c { /* u77 */
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compatible = "ti,ina226";
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reg = <0x4c>;
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shunt-resistor = <5000>;
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};
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ina226@4d { /* u73 */
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compatible = "ti,ina226";
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reg = <0x4d>;
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shunt-resistor = <5000>;
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};
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ina226@4e { /* u79 */
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compatible = "ti,ina226";
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reg = <0x4e>;
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shunt-resistor = <5000>;
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};
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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/* NC */
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
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#clock-cells = <0>;
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compatible = "infineon,irps5401";
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reg = <0x43>;
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};
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irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
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#clock-cells = <0>;
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compatible = "infineon,irps5401";
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reg = <0x44>;
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};
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irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
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#clock-cells = <0>;
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compatible = "infineon,irps5401";
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reg = <0x45>;
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};
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/* u68 IR38064 +0 */
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/* u70 IR38060 +1 */
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/* u74 IR38060 +2 */
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/* u75 IR38060 +6 */
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/* J19 header too */
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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/* SYSMON */
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};
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};
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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i2c-mux@74 { /* u26 */
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x74>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/*
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* IIC_EEPROM 1kB memory which uses 256B blocks
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* where every block has different address.
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* 0 - 256B address 0x54
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* 256B - 512B address 0x55
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* 512B - 768B address 0x56
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* 768B - 1024B address 0x57
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*/
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eeprom: eeprom@54 { /* u88 */
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compatible = "atmel,24c08";
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reg = <0x54>;
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};
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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si5341: clock-generator@36 { /* SI5341 - u46 */
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compatible = "si5341";
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reg = <0x36>;
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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si570_1: clock-generator@5d { /* USER SI570 - u47 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x5d>;
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temperature-stability = <50>;
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factory-fout = <300000000>;
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clock-frequency = <300000000>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x5d>;
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temperature-stability = <50>;
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factory-fout = <156250000>;
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clock-frequency = <148500000>;
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};
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};
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i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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si5328: clock-generator@69 { /* SI5328 - u48 */
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compatible = "silabs,si5328";
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reg = <0x69>;
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};
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};
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i2c@5 {
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#address-cells = <1>;
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|
#size-cells = <0>;
|
|
|
|
|
reg = <5>;
|
|
|
|
|
sc18is603@2f { /* sc18is602 - u93 */
|
|
|
|
|
compatible = "nxp,sc18is603";
|
|
|
|
|
reg = <0x2f>;
|
|
|
|
|
/* 4 gpios for CS not handled by driver */
|
|
|
|
|
/*
|
|
|
|
|
* USB2ANY cable or
|
|
|
|
|
* LMK04208 - u90 or
|
|
|
|
|
* LMX2594 - u102 or
|
|
|
|
|
* LMX2594 - u103 or
|
|
|
|
|
* LMX2594 - u104
|
|
|
|
|
*/
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
i2c@6 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <6>;
|
|
|
|
|
/* FMC connector */
|
|
|
|
|
};
|
|
|
|
|
/* 7 NC */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c-mux@75 {
|
|
|
|
|
compatible = "nxp,pca9548"; /* u27 */
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <0x75>;
|
|
|
|
|
|
|
|
|
|
i2c@0 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <0>;
|
|
|
|
|
/* FMCP_HSPC_IIC */
|
|
|
|
|
};
|
|
|
|
|
i2c@1 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <1>;
|
|
|
|
|
/* NC */
|
|
|
|
|
};
|
|
|
|
|
i2c@2 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <2>;
|
|
|
|
|
/* SYSMON */
|
|
|
|
|
};
|
|
|
|
|
i2c@3 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <3>;
|
|
|
|
|
/* DDR4 SODIMM */
|
|
|
|
|
dev@19 { /* u-boot detection FIXME */
|
|
|
|
|
compatible = "xxx";
|
|
|
|
|
reg = <0x19>;
|
|
|
|
|
};
|
|
|
|
|
dev@30 { /* u-boot detection */
|
|
|
|
|
compatible = "xxx";
|
|
|
|
|
reg = <0x30>;
|
|
|
|
|
};
|
|
|
|
|
dev@35 { /* u-boot detection */
|
|
|
|
|
compatible = "xxx";
|
|
|
|
|
reg = <0x35>;
|
|
|
|
|
};
|
|
|
|
|
dev@36 { /* u-boot detection */
|
|
|
|
|
compatible = "xxx";
|
|
|
|
|
reg = <0x36>;
|
|
|
|
|
};
|
|
|
|
|
dev@51 { /* u-boot detection - maybe SPD */
|
|
|
|
|
compatible = "xxx";
|
|
|
|
|
reg = <0x51>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
i2c@4 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <4>;
|
|
|
|
|
/* SFP3 */
|
|
|
|
|
};
|
|
|
|
|
i2c@5 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <5>;
|
|
|
|
|
/* SFP2 */
|
|
|
|
|
};
|
|
|
|
|
i2c@6 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <6>;
|
|
|
|
|
/* SFP1 */
|
|
|
|
|
};
|
|
|
|
|
i2c@7 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <7>;
|
|
|
|
|
/* SFP0 */
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&qspi {
|
|
|
|
|
status = "okay";
|
|
|
|
|
is-dual = <1>;
|
|
|
|
|
flash@0 {
|
|
|
|
|
compatible = "m25p80"; /* 32MB */
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
reg = <0x0>;
|
|
|
|
|
spi-tx-bus-width = <1>;
|
|
|
|
|
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
|
|
|
|
|
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
|
|
|
|
partition@qspi-fsbl-uboot { /* for testing purpose */
|
|
|
|
|
label = "qspi-fsbl-uboot";
|
|
|
|
|
reg = <0x0 0x100000>;
|
|
|
|
|
};
|
|
|
|
|
partition@qspi-linux { /* for testing purpose */
|
|
|
|
|
label = "qspi-linux";
|
|
|
|
|
reg = <0x100000 0x500000>;
|
|
|
|
|
};
|
|
|
|
|
partition@qspi-device-tree { /* for testing purpose */
|
|
|
|
|
label = "qspi-device-tree";
|
|
|
|
|
reg = <0x600000 0x20000>;
|
|
|
|
|
};
|
|
|
|
|
partition@qspi-rootfs { /* for testing purpose */
|
|
|
|
|
label = "qspi-rootfs";
|
|
|
|
|
reg = <0x620000 0x5E0000>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&rtc {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&sata {
|
|
|
|
|
status = "okay";
|
|
|
|
|
/* SATA OOB timing settings */
|
|
|
|
|
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
|
|
|
|
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
|
|
|
|
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
|
|
|
|
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
|
|
|
|
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
|
|
|
|
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
|
|
|
|
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
|
|
|
|
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
|
|
|
|
phy-names = "sata-phy";
|
|
|
|
|
phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* SD1 with level shifter */
|
|
|
|
|
&sdhci1 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
no-1-8-v;
|
|
|
|
|
disable-wp;
|
|
|
|
|
xlnx,mio_bank = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&serdes {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&uart0 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* ULPI SMSC USB3320 */
|
|
|
|
|
&usb0 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&dwc3_0 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
dr_mode = "host";
|
|
|
|
|
snps,usb3_lpm_capable;
|
|
|
|
|
phy-names = "usb3-phy";
|
|
|
|
|
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
|
|
|
|
|
};
|
