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/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _UART_H_
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#define _UART_H_
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/* UART registers */
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struct uart_ctlr {
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uint uart_thr_dlab_0; /* UART_THR_DLAB_0_0, offset 00 */
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uint uart_ier_dlab_0; /* UART_IER_DLAB_0_0, offset 04 */
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uint uart_iir_fcr; /* UART_IIR_FCR_0, offset 08 */
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uint uart_lcr; /* UART_LCR_0, offset 0C */
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uint uart_mcr; /* UART_MCR_0, offset 10 */
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uint uart_lsr; /* UART_LSR_0, offset 14 */
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uint uart_msr; /* UART_MSR_0, offset 18 */
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uint uart_spr; /* UART_SPR_0, offset 1C */
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uint uart_irda_csr; /* UART_IRDA_CSR_0, offset 20 */
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uint uart_reserved[6]; /* Reserved, unused, offset 24-38*/
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uint uart_asr; /* UART_ASR_0, offset 3C */
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};
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#define NVRM_PLLP_FIXED_FREQ_KHZ 216000
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#define NV_DEFAULT_DEBUG_BAUD 115200
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#define UART_FCR_TRIGGER_3 0x30 /* Mask for trigger set at 3 */
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#endif /* UART_H */
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