upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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93 lines
1.8 KiB
93 lines
1.8 KiB
10 years ago
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* FSL DCU Framebuffer driver
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/io.h>
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#include <common.h>
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#include <fsl_dcu_fb.h>
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#include <i2c.h>
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#include "div64.h"
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#include "../common/diu_ch7301.h"
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#include "ls1021aqds_qixis.h"
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DECLARE_GLOBAL_DATA_PTR;
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static int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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unsigned int dcu_set_pixel_clock(unsigned int pixclock)
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{
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unsigned long long div;
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div = (unsigned long long)(gd->bus_clk / 1000);
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div *= (unsigned long long)pixclock;
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do_div(div, 1000000000);
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return div;
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}
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int platform_dcu_init(unsigned int xres, unsigned int yres,
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const char *port,
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struct fb_videomode *dcu_fb_videomode)
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{
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const char *name;
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unsigned int pixel_format;
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int ret;
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u8 ch;
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/* Mux I2C3+I2C4 as HSYNC+VSYNC */
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ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
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1, &ch, 1);
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if (ret) {
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printf("Error: failed to read I2C @%02x\n",
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CONFIG_SYS_I2C_QIXIS_ADDR);
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return ret;
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}
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ch &= 0x1F;
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ch |= 0xA0;
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ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
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1, &ch, 1);
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if (ret) {
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printf("Error: failed to write I2C @%02x\n",
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CONFIG_SYS_I2C_QIXIS_ADDR);
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return ret;
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}
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if (strncmp(port, "hdmi", 4) == 0) {
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unsigned long pixval;
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name = "HDMI";
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pixval = 1000000000 / dcu_fb_videomode->pixclock;
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pixval *= 1000;
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i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
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select_i2c_ch_pca9547(I2C_MUX_CH_CH7301);
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diu_set_dvi_encoder(pixval);
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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} else {
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return 0;
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}
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printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
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pixel_format = 32;
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fsl_dcu_init(xres, yres, pixel_format);
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return 0;
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}
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