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/*
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* (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
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*
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* Slight modifications made to support the SMN42 board from Siemens.
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* 2007 Gary Jennejohn garyj@denx.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/hardware.h>
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/* some parameters for the board */
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/* setting up the CPU-internal memory */
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#define SRAM_START 0x40000000
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#define SRAM_SIZE 0x00004000
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#define BCFG0_VALUE 0x1000ffef
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#define BCFG1_VALUE 0x10005D2F
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#define BCFG2_VALUE 0x10005D2F
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/*
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* For P0.18 to set ZZ to the SRAMs to 1. Also set P0.2 (SCL) and P0.3 (SDA)
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* for the bit-banger I2C driver correctly.
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*/
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#define IO0_VALUE 0x4000C
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_TEXT_BASE:
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.word CONFIG_SYS_TEXT_BASE
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MEMMAP_ADR:
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.word MEMMAP
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BCFG0_ADR:
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.word BCFG0
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_BCFG0_VALUE:
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.word BCFG0_VALUE
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BCFG1_ADR:
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.word BCFG1
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_BCFG1_VALUE:
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.word BCFG1_VALUE
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BCFG2_ADR:
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.word BCFG2
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_BCFG2_VALUE:
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.word BCFG2_VALUE
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IO0DIR_ADR:
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.word IO0DIR
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_IO0DIR_VALUE:
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.word IO0_VALUE
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IO0SET_ADR:
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.word IO0SET
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_IO0SET_VALUE:
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.word IO0_VALUE
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PINSEL2_ADR:
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.word PINSEL2
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PINSEL2_MASK:
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.word 0x00000000
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PINSEL2_VALUE:
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.word 0x0F804914
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.extern _start
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.globl lowlevel_init
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lowlevel_init:
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/* set up memory control register for bank 0 */
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ldr r0, _BCFG0_VALUE
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ldr r1, BCFG0_ADR
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str r0, [r1]
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/* set up memory control register for bank 1 */
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ldr r0, _BCFG1_VALUE
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ldr r1, BCFG1_ADR
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str r0, [r1]
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/* set up memory control register for bank 2 */
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ldr r0, _BCFG2_VALUE
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ldr r1, BCFG2_ADR
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str r0, [r1]
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/* set IO0DIR to make P0.2, P0.3 and P0.18 outputs */
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ldr r0, _IO0DIR_VALUE
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ldr r1, IO0DIR_ADR
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str r0, [r1]
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/* set P0.18 to 1 */
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ldr r0, _IO0SET_VALUE
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ldr r1, IO0SET_ADR
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str r0, [r1]
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/* set up PINSEL2 for bus-pins */
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ldr r0, PINSEL2_ADR
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ldr r1, [r0]
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ldr r2, PINSEL2_MASK
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ldr r3, PINSEL2_VALUE
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and r1, r1, r2
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orr r1, r1, r3
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str r1, [r0]
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/* move vectors to beginning of SRAM */
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mov r2, #SRAM_START
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mov r0, #0 /*_start*/
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ldmneia r0!, {r3-r10}
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stmneia r2!, {r3-r10}
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ldmneia r0, {r3-r9}
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stmneia r2, {r3-r9}
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/* Set-up MEMMAP register, so vectors are taken from SRAM */
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ldr r0, MEMMAP_ADR
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mov r1, #0x02 /* vectors re-mapped to static RAM */
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str r1, [r0]
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/* everything is fine now */
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mov pc, lr
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