upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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122 lines
4.6 KiB
122 lines
4.6 KiB
21 years ago
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/*
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* include/asm-armnommu/arch-netarm/netarm_eni_module.h
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*
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* Copyright (C) 2000 NETsilicon, Inc.
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* Copyright (C) 2000 WireSpeed Communications Corporation
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*
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* This software is copyrighted by WireSpeed. LICENSEE agrees that
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* it will not delete this copyright notice, trademarks or protective
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* notices from any copy made by LICENSEE.
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*
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* This software is provided "AS-IS" and any express or implied
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* warranties or conditions, including but not limited to any
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* implied warranties of merchantability and fitness for a particular
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* purpose regarding this software. In no event shall WireSpeed
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* be liable for any indirect, consequential, or incidental damages,
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* loss of profits or revenue, loss of use or data, or interruption
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* of business, whether the alleged damages are labeled in contract,
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* tort, or indemnity.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* author(s) : David Smith
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*/
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#ifndef __NETARM_ENI_MODULE_REGISTERS_H
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#define __NETARM_ENI_MODULE_REGISTERS_H
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/* ENI unit register offsets */
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/* #ifdef CONFIG_ARCH_NETARM */
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#define NETARM_ENI_MODULE_BASE (0xFFA00000)
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/* #endif / * CONFIG_ARCH_NETARM */
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#define get_eni_reg_addr(c) ((volatile unsigned int *)(NETARM_ENI_MODULE_BASE + (c)))
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#define get_eni_ctl_reg_addr(minor) \
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(get_eni_reg_addr(NETARM_ENI_1284_PORT1_CONTROL) + (minor))
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#define NETARM_ENI_GENERAL_CONTROL (0x00)
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#define NETARM_ENI_STATUS_CONTROL (0x04)
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#define NETARM_ENI_FIFO_MODE_DATA (0x08)
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#define NETARM_ENI_1284_PORT1_CONTROL (0x10)
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#define NETARM_ENI_1284_PORT2_CONTROL (0x14)
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#define NETARM_ENI_1284_PORT3_CONTROL (0x18)
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#define NETARM_ENI_1284_PORT4_CONTROL (0x1c)
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#define NETARM_ENI_1284_CHANNEL1_DATA (0x20)
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#define NETARM_ENI_1284_CHANNEL2_DATA (0x24)
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#define NETARM_ENI_1284_CHANNEL3_DATA (0x28)
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#define NETARM_ENI_1284_CHANNEL4_DATA (0x2c)
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#define NETARM_ENI_ENI_CONTROL (0x30)
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#define NETARM_ENI_ENI_PULSED_INTR (0x34)
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#define NETARM_ENI_ENI_SHARED_RAM_ADDR (0x38)
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#define NETARM_ENI_ENI_SHARED (0x3c)
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/* select bitfield defintions */
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/* General Control Register (0xFFA0_0000) */
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#define NETARM_ENI_GCR_ENIMODE_IEEE1284 (0x00000001)
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#define NETARM_ENI_GCR_ENIMODE_SHRAM16 (0x00000004)
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#define NETARM_ENI_GCR_ENIMODE_SHRAM8 (0x00000005)
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#define NETARM_ENI_GCR_ENIMODE_FIFO16 (0x00000006)
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#define NETARM_ENI_GCR_ENIMODE_FIFO8 (0x00000007)
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#define NETARM_ENI_GCR_ENIMODE_MASK (0x00000007)
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/* IEEE 1284 Port Control Registers 1-4 (0xFFA0_0010, 0xFFA0_0014,
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0xFFA0_0018, 0xFFA0_001c) */
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#define NETARM_ENI_1284PC_PORT_ENABLE (0x80000000)
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#define NETARM_ENI_1284PC_DMA_ENABLE (0x40000000)
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#define NETARM_ENI_1284PC_OBE_INT_EN (0x20000000)
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#define NETARM_ENI_1284PC_ACK_INT_EN (0x10000000)
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#define NETARM_ENI_1284PC_ECP_MODE (0x08000000)
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#define NETARM_ENI_1284PC_LOOPBACK_MODE (0x04000000)
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#define NETARM_ENI_1284PC_STROBE_TIME0 (0x00000000) /* 0.5 uS */
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#define NETARM_ENI_1284PC_STROBE_TIME1 (0x01000000) /* 1.0 uS */
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#define NETARM_ENI_1284PC_STROBE_TIME2 (0x02000000) /* 5.0 uS */
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#define NETARM_ENI_1284PC_STROBE_TIME3 (0x03000000) /* 10.0 uS */
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#define NETARM_ENI_1284PC_STROBE_MASK (0x03000000)
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#define NETARM_ENI_1284PC_MAN_STROBE_EN (0x00800000)
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#define NETARM_ENI_1284PC_FAST_MODE (0x00400000)
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#define NETARM_ENI_1284PC_BIDIR_MODE (0x00200000)
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#define NETARM_ENI_1284PC_MAN_STROBE (0x00080000)
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#define NETARM_ENI_1284PC_AUTO_FEED (0x00040000)
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#define NETARM_ENI_1284PC_INIT (0x00020000)
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#define NETARM_ENI_1284PC_HSELECT (0x00010000)
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#define NETARM_ENI_1284PC_FE_INT_EN (0x00008000)
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#define NETARM_ENI_1284PC_EPP_MODE (0x00004000)
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#define NETARM_ENI_1284PC_IBR_INT_EN (0x00002000)
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#define NETARM_ENI_1284PC_IBR (0x00001000)
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#define NETARM_ENI_1284PC_RXFDB_1BYTE (0x00000400)
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#define NETARM_ENI_1284PC_RXFDB_2BYTE (0x00000800)
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#define NETARM_ENI_1284PC_RXFDB_3BYTE (0x00000c00)
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#define NETARM_ENI_1284PC_RXFDB_4BYTE (0x00000000)
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#define NETARM_ENI_1284PC_RBCC (0x00000200)
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#define NETARM_ENI_1284PC_RBCT (0x00000100)
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#define NETARM_ENI_1284PC_ACK (0x00000080)
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#define NETARM_ENI_1284PC_FIFO_E (0x00000040)
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#define NETARM_ENI_1284PC_OBE (0x00000020)
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#define NETARM_ENI_1284PC_ACK_INT (0x00000010)
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#define NETARM_ENI_1284PC_BUSY (0x00000008)
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#define NETARM_ENI_1284PC_PE (0x00000004)
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#define NETARM_ENI_1284PC_PSELECT (0x00000002)
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#define NETARM_ENI_1284PC_FAULT (0x00000001)
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#endif /* __NETARM_ENI_MODULE_REGISTERS_H */
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