upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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79 lines
2.4 KiB
79 lines
2.4 KiB
19 years ago
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/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2006
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* DAVE Srl <www.dave-tech.it>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _SDRAM_H_
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#define _SDRAM_H_
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#include <config.h>
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#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
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#define ONE_BILLION 1000000000
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struct sdram_conf_s {
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unsigned long size;
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int rows;
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unsigned long reg;
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};
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typedef struct sdram_conf_s sdram_conf_t;
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/* Bitfields offsets */
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#define SDRAM0_TR_CASL (31 - 8)
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#define SDRAM0_TR_PTA (31 - 13)
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#define SDRAM0_TR_CTP (31 - 15)
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#define SDRAM0_TR_LDF (31 - 17)
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#define SDRAM0_TR_RFTA (31 - 29)
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#define SDRAM0_TR_RCD (31 - 31)
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#ifdef CFG_SDRAM_CL
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/* SDRAM timings [ns] according to AMCC/IBM names (see SDRAM_faq.doc) */
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#define CFG_SDRAM_CASL CFG_SDRAM_CL
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#define CFG_SDRAM_PTA CFG_SDRAM_tRP
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#define CFG_SDRAM_CTP (CFG_SDRAM_tRC - CFG_SDRAM_tRCD - CFG_SDRAM_tRP)
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#define CFG_SDRAM_LDF 0
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#ifdef CFG_SDRAM_tRFC
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#define CFG_SDRAM_RFTA CFG_SDRAM_tRFC
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#else
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#define CFG_SDRAM_RFTA CFG_SDRAM_tRC
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#endif
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#define CFG_SDRAM_RCD CFG_SDRAM_tRCD
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#endif /* #ifdef CFG_SDRAM_CL */
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/*
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* Some defines for the 440 DDR controller
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*/
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#define SDRAM_CFG0_DC_EN 0x80000000 /* SDRAM Controller Enable */
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#define SDRAM_CFG0_MEMCHK 0x30000000 /* Memory data error checking mask*/
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#define SDRAM_CFG0_MEMCHK_NON 0x00000000 /* No ECC generation */
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#define SDRAM_CFG0_MEMCHK_GEN 0x20000000 /* ECC generation */
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#define SDRAM_CFG0_MEMCHK_CHK 0x30000000 /* ECC generation and checking */
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#define SDRAM_CFG0_DRAMWDTH 0x02000000 /* DRAM width mask */
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#define SDRAM_CFG0_DRAMWDTH_32 0x00000000 /* 32 bits */
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#define SDRAM_CFG0_DRAMWDTH_64 0x02000000 /* 64 bits */
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#endif
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