upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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75 lines
1.9 KiB
75 lines
1.9 KiB
15 years ago
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/*
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* (C) Copyright 2010
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* Matthias Weisser <weisserm@arcor.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef ASM_OFFSETS_H
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#define ASM_OFFSETS_H
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/*
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* Offset definitions for DDR controller
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*/
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#define DDR2_DRIC 0x00
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#define DDR2_DRIC1 0x02
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#define DDR2_DRIC2 0x04
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#define DDR2_DRCA 0x06
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#define DDR2_DRCM 0x08
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#define DDR2_DRCST1 0x0a
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#define DDR2_DRCST2 0x0c
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#define DDR2_DRCR 0x0e
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#define DDR2_DRCF 0x20
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#define DDR2_DRASR 0x30
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#define DDR2_DRIMS 0x50
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#define DDR2_DROS 0x60
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#define DDR2_DRIBSODT1 0x64
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#define DDR2_DROABA 0x70
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#define DDR2_DROBS 0x84
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/*
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* Offset definitions Chip Control Module
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*/
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#define CCNT_CDCRC 0xec
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/*
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* Offset definitions clock reset generator
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*/
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#define CRG_CRPR 0x00
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#define CRG_CRHA 0x18
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#define CRG_CRPA 0x1c
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#define CRG_CRPB 0x20
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#define CRG_CRHB 0x24
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#define CRG_CRAM 0x28
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/*
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* Offset definitions External bus interface
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*/
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#define MEMC_MCFMODE0 0x00
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#define MEMC_MCFMODE2 0x08
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#define MEMC_MCFMODE4 0x10
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#define MEMC_MCFTIM0 0x20
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#define MEMC_MCFTIM2 0x28
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#define MEMC_MCFTIM4 0x30
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#define MEMC_MCFAREA0 0x40
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#define MEMC_MCFAREA2 0x48
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#define MEMC_MCFAREA4 0x50
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#endif /* ASM_OFFSETS_H */
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