upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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80 lines
2.4 KiB
80 lines
2.4 KiB
15 years ago
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/*
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* Auther:
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* Vaibhav Hiremath <hvaibhav@ti.com>
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*
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* Copyright (C) 2010
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* Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _EMIF_H_
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#define _EMIF_H_
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/*
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* Configuration values
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*/
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#define EMIF4_TIM1_T_RP (0x3 << 25)
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#define EMIF4_TIM1_T_RCD (0x3 << 21)
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#define EMIF4_TIM1_T_WR (0x3 << 17)
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#define EMIF4_TIM1_T_RAS (0x8 << 12)
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#define EMIF4_TIM1_T_RC (0xA << 6)
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#define EMIF4_TIM1_T_RRD (0x2 << 3)
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#define EMIF4_TIM1_T_WTR (0x2)
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#define EMIF4_TIM2_T_XP (0x2 << 28)
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#define EMIF4_TIM2_T_ODT (0x0 << 25)
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#define EMIF4_TIM2_T_XSNR (0x1C << 16)
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#define EMIF4_TIM2_T_XSRD (0xC8 << 6)
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#define EMIF4_TIM2_T_RTP (0x1 << 3)
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#define EMIF4_TIM2_T_CKE (0x2)
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#define EMIF4_TIM3_T_RFC (0x25 << 4)
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#define EMIF4_TIM3_T_RAS_MAX (0x7)
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#define EMIF4_PWR_IDLE_MODE (0x2 << 30)
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#define EMIF4_PWR_DPD_DIS (0x0 << 10)
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#define EMIF4_PWR_DPD_EN (0x1 << 10)
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#define EMIF4_PWR_LP_MODE (0x0 << 8)
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#define EMIF4_PWR_PM_TIM (0x0)
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#define EMIF4_INITREF_DIS (0x0 << 31)
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#define EMIF4_REFRESH_RATE (0x50F)
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#define EMIF4_CFG_SDRAM_TYP (0x2 << 29)
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#define EMIF4_CFG_IBANK_POS (0x0 << 27)
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#define EMIF4_CFG_DDR_TERM (0x0 << 24)
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#define EMIF4_CFG_DDR2_DDQS (0x1 << 23)
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#define EMIF4_CFG_DDR_DIS_DLL (0x0 << 20)
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#define EMIF4_CFG_SDR_DRV (0x0 << 18)
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#define EMIF4_CFG_NARROW_MD (0x0 << 14)
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#define EMIF4_CFG_CL (0x5 << 10)
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#define EMIF4_CFG_ROWSIZE (0x0 << 7)
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#define EMIF4_CFG_IBANK (0x3 << 4)
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#define EMIF4_CFG_EBANK (0x0 << 3)
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#define EMIF4_CFG_PGSIZE (0x2)
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/*
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* EMIF4 PHY Control 1 register configuration
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*/
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#define EMIF4_DDR1_EXT_STRB_EN (0x1 << 7)
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#define EMIF4_DDR1_EXT_STRB_DIS (0x0 << 7)
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#define EMIF4_DDR1_PWRDN_DIS (0x0 << 6)
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#define EMIF4_DDR1_PWRDN_EN (0x1 << 6)
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#define EMIF4_DDR1_READ_LAT (0x6 << 0)
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#endif /* endif _EMIF_H_ */
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