upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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71 lines
2.4 KiB
71 lines
2.4 KiB
11 years ago
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/*
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* Copyright (C) 2013 Boundary Devices
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* ZQ Calibration */
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DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
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DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
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DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
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DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
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DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
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DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
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/*
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* DQS gating, read delay, write delay calibration values
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* based on calibration compare of 0x00ffff00
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*/
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DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E
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DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200
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DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202
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DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172
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DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C
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DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49
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DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133
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DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E
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/* read data bit delay */
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DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
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/* Complete calibration by forced measurment */
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DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
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DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
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/* in DDR3, 64-bit mode, only MMDC0 is initiated */
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DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
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DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
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DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323
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DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63
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DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
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DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
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DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
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DATA 4, MX6_MMDC_P0_MDOR, 0x00440e21
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DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
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DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
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/* MR2 */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
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DATA 4, MX6_MMDC_P0_MDSCR, 0x0400803a
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/* MR3 */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
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DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b
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/* MR1 */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
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/* MR0 */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x07208030
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DATA 4, MX6_MMDC_P0_MDSCR, 0x07208038
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/* ZQ calibration */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
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/* final ddr setup */
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DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
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DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
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DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000007
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DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
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DATA 4, MX6_MMDC_P1_MAPSR, 0x00011006
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
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