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/*
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* Copyright (C) ST-Ericsson SA 2009
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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/* Peripheral clusters */
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#define U8500_PER3_BASE 0x80000000
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#define U8500_PER2_BASE 0x80110000
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#define U8500_PER1_BASE 0x80120000
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#define U8500_PER4_BASE 0x80150000
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#define U8500_PER6_BASE 0xa03c0000
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#define U8500_PER7_BASE 0xa03d0000
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#define U8500_PER5_BASE 0xa03e0000
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/* GPIO */
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#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
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#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xE000 + 0x80)
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#define U8500_GPIO2_BASE (U8500_PER3_BASE + 0xE000)
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#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xE000 + 0x80)
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#define U8500_GPIO4_BASE (U8500_PER3_BASE + 0xE000 + 0x100)
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#define U8500_GPIO5_BASE (U8500_PER3_BASE + 0xE000 + 0x180)
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#define U8500_GPIO6_BASE (U8500_PER2_BASE + 0xE000)
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#define U8500_GPIO7_BASE (U8500_PER2_BASE + 0xE000 + 0x80)
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#define U8500_GPIO8_BASE (U8500_PER5_BASE + 0x1E000)
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/* Per7 */
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#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000)
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/* Per6 */
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#define U8500_MTU0_BASE_V1 (U8500_PER6_BASE + 0x6000)
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#define U8500_MTU1_BASE_V1 (U8500_PER6_BASE + 0x7000)
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#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
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/* Per5 */
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#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
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/* Per4 */
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#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
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#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
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/* Per3 */
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#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
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#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
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/* Per2 */
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#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
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/* Per1 */
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#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
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#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
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#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
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/* Last page of Boot ROM */
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#define U8500_BOOTROM_BASE 0x90000000
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#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOTROM_BASE + 0x1FFF4)
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#define U8500_ASIC_ID_LOC_V2 (U8500_BOOTROM_BASE + 0x1DBF4)
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/* AB8500 specifics */
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/* address bank */
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#define AB8500_REGU_CTRL2 0x0004
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#define AB8500_MISC 0x0010
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/* registers */
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#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A
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#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421
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#define AB8500_REV_REG 0x1080
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#define AB8500_GPIO_SEL2_REG 0x1001
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#define AB8500_GPIO_DIR2_REG 0x1011
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#define AB8500_GPIO_DIR4_REG 0x1013
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#define AB8500_GPIO_SEL4_REG 0x1003
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#define AB8500_GPIO_OUT2_REG 0x1021
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#define AB8500_GPIO_OUT4_REG 0x1023
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#define LDO_VAUX3_ENABLE_MASK 0x3
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#define LDO_VAUX3_ENABLE_VAL 0x1
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#define LDO_VAUX3_SEL_MASK 0xf
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#define LDO_VAUX3_SEL_2V9 0xd
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#define LDO_VAUX3_V2_SEL_MASK 0x7
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#define LDO_VAUX3_V2_SEL_2V91 0x7
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#endif /* __ASM_ARCH_HARDWARE_H */
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