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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_CACHE_H
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#define _ASM_CACHE_H
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#include <asm/system.h>
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#ifndef CONFIG_ARM64
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/*
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* Invalidate L2 Cache using co-proc instruction
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*/
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static inline void invalidate_l2_cache(void)
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{
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unsigned int val=0;
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asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
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: : "r" (val) : "cc");
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isb();
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}
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void l2_cache_enable(void);
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void l2_cache_disable(void);
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void set_section_dcache(int section, enum dcache_option option);
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void arm_init_before_mmu(void);
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void arm_init_domains(void);
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void cpu_cache_initialization(void);
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void dram_bank_mmu_setup(int bank);
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#endif
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/*
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* The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
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* use that value for aligning DMA buffers unless the board config has specified
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* an alternate cache line size.
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*/
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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#else
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#define ARCH_DMA_MINALIGN 64
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#endif
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#endif /* _ASM_CACHE_H */
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