upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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246 lines
7.6 KiB
246 lines
7.6 KiB
19 years ago
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/**
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* @file IxEthAccDataPlane_p.h
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*
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* @author Intel Corporation
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* @date 12-Feb-2002
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*
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* @brief Internal Header file for IXP425 Ethernet Access component.
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*
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* Design Notes:
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*
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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#ifndef IxEthAccDataPlane_p_H
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#define IxEthAccDataPlane_p_H
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#include <IxOsal.h>
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#include <IxQMgr.h>
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/**
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* @addtogroup IxEthAccPri
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*@{
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*/
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/* typedefs global to this file*/
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typedef struct
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{
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IX_OSAL_MBUF *pHead;
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IX_OSAL_MBUF *pTail;
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}IxEthAccDataPlaneQList;
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/**
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* @struct IxEthAccDataPlaneStats
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* @brief Statistics data structure associated with the data plane
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*
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*/
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typedef struct
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{
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UINT32 addToSwQ;
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UINT32 removeFromSwQ;
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UINT32 unchainedTxMBufs;
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UINT32 chainedTxMBufs;
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UINT32 unchainedTxDoneMBufs;
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UINT32 chainedTxDoneMBufs;
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UINT32 unchainedRxMBufs;
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UINT32 chainedRxMBufs;
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UINT32 unchainedRxFreeMBufs;
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UINT32 chainedRxFreeMBufs;
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UINT32 rxCallbackCounter;
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UINT32 rxCallbackBurstRead;
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UINT32 txDoneCallbackCounter;
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UINT32 unexpectedError;
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} IxEthAccDataPlaneStats;
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/**
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* @fn ixEthAccMbufFromSwQ
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* @brief used during disable steps to convert mbufs from
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* swq format, ready to be pushed into hw queues for NPE,
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* back into XScale format
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*/
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IX_OSAL_MBUF *ixEthAccMbufFromSwQ(IX_OSAL_MBUF *mbuf);
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/**
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* @fn ixEthAccDataPlaneShow
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* @brief Show function (for data plane statistics
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*/
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void ixEthAccDataPlaneShow(void);
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/*
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* lock dataplane when atomic operation is required
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*/
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#define IX_ETH_ACC_DATA_PLANE_LOCK(arg) arg = ixOsalIrqLock();
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#define IX_ETH_ACC_DATA_PLANE_UNLOCK(arg) ixOsalIrqUnlock(arg);
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/*
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* Use MBUF fields
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*/
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#define IX_ETHACC_NE_SHARED(mBufPtr) \
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((IxEthAccNe *)&((mBufPtr)->ix_ne))
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#if 1
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#define IX_ETHACC_NE_NEXT(mBufPtr) (mBufPtr)->ix_ne.reserved[0]
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/* tm - wrong!! len and pkt_len are in the second word - #define IX_ETHACC_NE_LEN(mBufPtr) (mBufPtr)->ix_ne.reserved[3] */
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#define IX_ETHACC_NE_LEN(mBufPtr) (mBufPtr)->ix_ne.reserved[1]
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#define IX_ETHACC_NE_DATA(mBufPtr)(mBufPtr)->ix_ne.reserved[2]
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#else
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#define IX_ETHACC_NE_NEXT(mBufPtr) \
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IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_next
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#define IX_ETHACC_NE_LEN(mBufPtr) \
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IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_lengths
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#define IX_ETHACC_NE_DATA(mBufPtr) \
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IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_data
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#endif
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/*
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* Use MBUF next pointer field to chain data.
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*/
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#define IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER(mbuf) (mbuf)->ix_ctrl.ix_chain
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#define IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(mbuf_list) ((mbuf_list.pHead) == NULL)
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#define IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(mbuf_list,mbuf_to_add) \
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do { \
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int lockVal; \
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IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \
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IX_ETH_ACC_STATS_INC(ixEthAccDataStats.addToSwQ); \
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if ( (mbuf_list.pHead) != NULL ) \
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{ \
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(IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add))) = (mbuf_list.pHead);\
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(mbuf_list.pHead) = (mbuf_to_add); \
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} \
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else { \
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(mbuf_list.pTail) = (mbuf_list.pHead) = (mbuf_to_add); \
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IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \
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} \
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IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \
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} while(0)
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#define IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(mbuf_list,mbuf_to_add) \
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do { \
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int lockVal; \
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IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \
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IX_ETH_ACC_STATS_INC(ixEthAccDataStats.addToSwQ); \
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if ( (mbuf_list.pHead) == NULL ) \
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{ \
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(mbuf_list.pHead) = mbuf_to_add; \
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IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \
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} \
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else { \
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IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_list.pTail)) = (mbuf_to_add); \
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IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \
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} \
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(mbuf_list.pTail) = mbuf_to_add; \
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IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \
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} while (0)
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#define IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(mbuf_list,mbuf_to_rem) \
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do { \
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int lockVal; \
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IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \
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if ( (mbuf_list.pHead) != NULL ) \
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{ \
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IX_ETH_ACC_STATS_INC(ixEthAccDataStats.removeFromSwQ); \
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(mbuf_to_rem) = (mbuf_list.pHead) ; \
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(mbuf_list.pHead) = (IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_rem)));\
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} \
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else { \
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(mbuf_to_rem) = NULL; \
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} \
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IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \
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} while (0)
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/**
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* @brief message handler QManager entries for NPE id => port ID conversion (NPE_B => 0, NPE_C => 1)
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*/
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#define IX_ETH_ACC_PORT_TO_NPE_ID(port) \
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ixEthAccPortData[(port)].npeId
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#define IX_ETH_ACC_NPE_TO_PORT_ID(npe) ((npe == 0 ? 2 : (npe == 1 ? 0 : ( npe == 2 ? 1 : -1 ))))
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#define IX_ETH_ACC_PORT_TO_TX_Q_ID(port) \
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ixEthAccPortData[(port)].ixEthAccTxData.txQueue
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#define IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(port) \
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ixEthAccPortData[(port)].ixEthAccRxData.rxFreeQueue
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#define IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(port) (port == IX_ETH_PORT_1 ? IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE : (port == IX_ETH_PORT_2 ? IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE : IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE))
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#define IX_ETH_ACC_PORT_TO_RX_FREE_Q_SOURCE(port) (port == IX_ETH_PORT_1 ? IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE : (port == IX_ETH_PORT_2 ? IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE : IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE ))
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/* Flush the mbufs chain and all data pointed to by the mbuf */
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#ifndef NDEBUG
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#define IX_ETH_ACC_STATS_INC(x) (x++)
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#else
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#define IX_ETH_ACC_STATS_INC(x)
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#endif
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#define IX_ETH_ACC_MAX_TX_FRAMES_TO_SUBMIT 128
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void ixEthRxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId);
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void ixEthRxMultiBufferQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId);
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void ixEthTxFrameDoneQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId);
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#endif /* IxEthAccDataPlane_p_H */
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/**
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*@}
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*/
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