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/*
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* (C) Copyright 2009-2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <ppc_asm.tmpl>
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#include <config.h>
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#include <asm/mmu.h>
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#include <asm/ppc4xx.h>
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/*
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* TLB TABLE
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*
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* This table is used by the cpu boot code to setup the initial tlb
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* entries. Rather than make broad assumptions in the cpu source tree,
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* this table lets each board set things up however they like.
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*
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* Pointer to the table is returned in r1
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*
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*/
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.section .bootpg,"ax"
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.globl tlbtab
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tlbtab:
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tlbtab_start
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/*
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* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
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* use the speed up boot process. It is patched after relocation to
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* enable SA_I.
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*/
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tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
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4, AC_RWX | SA_G) /* TLB 0 */
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/*
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* TLB entries for SDRAM are not needed on this platform.
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* They are dynamically generated in the SPD DDR(2) detection
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* routine.
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*/
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tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4,
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AC_RWX | SA_I)
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tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K,
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CONFIG_SYS_ACE_BASE_PHYS_L, CONFIG_SYS_ACE_BASE_PHYS_H,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD,
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AC_RW | SA_IG)
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tlbtab_end
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