upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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441 lines
13 KiB
441 lines
13 KiB
21 years ago
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/*
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* (C) Copyright 2003
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* Denis Peter, d.peter@mpl.ch
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* MACROS and register definitions for PATI Registers
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************************************************************************/
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#ifndef __PATI_H_
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#define __PATI_H_ 1
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#define PLD_PART_ID 0x0
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#define PLD_BOARD_TIMING 0x4
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#define PLD_CONF_REG1 0x8
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#define PLD_CONF_REG2 0xC
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#define PLD_CONF_RES 0x10
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#define SET_REG_BIT(y,x) (y<<(31-x))
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#define GET_REG_BIT(y,x) ((y>>(31-x)) & 0x1L)
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/* SDRAM Controller PLD_PART_ID */
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/* 9 10 11 12 13 14 19 31 */
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#define SDRAM_PART3 9
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#define SDRAM_PART2 10
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#define SDRAM_PART1 11
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#define SDRAM_PART0 12
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#define SDRAM_ID3 13
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#define SDRAM_ID2 14
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#define SDRAM_ID1 19
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#define SDRAM_ID0 31
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#define SDRAM_PART(x) ( \
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(GET_REG_BIT(x,SDRAM_PART3)<<3) |\
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(GET_REG_BIT(x,SDRAM_PART2)<<2) |\
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(GET_REG_BIT(x,SDRAM_PART1)<<1) |\
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(GET_REG_BIT(x,SDRAM_PART0)))
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#define SDRAM_ID(x) ( \
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(GET_REG_BIT(x,SDRAM_ID3)<<3) |\
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(GET_REG_BIT(x,SDRAM_ID2)<<2) |\
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(GET_REG_BIT(x,SDRAM_ID1)<<1) |\
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(GET_REG_BIT(x,SDRAM_ID0)))
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/* System Controller */
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/* 0 1 3 4 5 16 20 28 29 30 */
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#define SYSCNTR_PART4 0
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#define SYSCNTR_PART3 1
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#define SYSCNTR_PART2 3
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#define SYSCNTR_PART1 4
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#define SYSCNTR_PART0 5
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#define SYSCNTR_ID4 16
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#define SYSCNTR_ID3 20
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#define SYSCNTR_ID2 28
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#define SYSCNTR_ID1 29
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#define SYSCNTR_ID0 30
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#define SYSCNTR_PART(x) ( \
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(GET_REG_BIT(x,SYSCNTR_PART4)<<4) |\
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(GET_REG_BIT(x,SYSCNTR_PART3)<<3) |\
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(GET_REG_BIT(x,SYSCNTR_PART2)<<2) |\
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(GET_REG_BIT(x,SYSCNTR_PART1)<<1) |\
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(GET_REG_BIT(x,SYSCNTR_PART0)))
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#define SYSCNTR_ID(x) ( \
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(GET_REG_BIT(x,SYSCNTR_ID4)<<4) |\
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(GET_REG_BIT(x,SYSCNTR_ID3)<<3) |\
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(GET_REG_BIT(x,SYSCNTR_ID2)<<2) |\
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(GET_REG_BIT(x,SYSCNTR_ID1)<<1) |\
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(GET_REG_BIT(x,SYSCNTR_ID0)))
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/* SDRAM Controller PLD_BOARD_TIMING */
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/* 9 10 11 12 13 14 19 31 */
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#define SDRAM_CAL 9
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#define SDRAM_RCD 10
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#define SDRAM_WREQ 11
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#define SDRAM_PR 12
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#define SDRAM_RC 13
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#define SDRAM_LMR 14
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#define SDRAM_IIP 19
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#define SDRAM_RES0 31
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/* System Controller */
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/* 0 1 3 4 5 16 20 28 29 30 */
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#define SYSCNTR_BREV0 0
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#define SYSCNTR_BREV1 1
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#define SYSCNTR_BREV2 3
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#define SYSCNTR_BREV3 4
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#define SYSCNTR_RES0 5
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#define SYSCNTR_RES1 16
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#define SYSCNTR_RES2 20
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#define SYSCNTR_FLWAIT2 28
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#define SYSCNTR_FLWAIT1 29
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#define SYSCNTR_FLWAIT0 30
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#define SYSCNTR_BREV(x) ( \
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(GET_REG_BIT(x,SYSCNTR_BREV3)<<3) |\
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(GET_REG_BIT(x,SYSCNTR_BREV2)<<2) |\
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(GET_REG_BIT(x,SYSCNTR_BREV1)<<1) |\
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(GET_REG_BIT(x,SYSCNTR_BREV0)))
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#define GET_SYSCNTR_FLWAIT(x) ( \
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(GET_REG_BIT(x,SYSCNTR_FLWAIT2)<<2) |\
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(GET_REG_BIT(x,SYSCNTR_FLWAIT1)<<1) |\
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(GET_REG_BIT(x,SYSCNTR_FLWAIT0)))
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#define SET_SYSCNTR_FLWAIT(x) ( \
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(SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_FLWAIT2)) |\
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(SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_FLWAIT1)) |\
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(SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_FLWAIT0)))
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/* SDRAM Controller REG 2*/
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/* 9 10 11 12 13 14 19 31 */
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#define SDRAM_MUX0 9
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#define SDRAM_MUX1 10
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#define SDRAM_PDIS 11
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#define SDRAM_RES1 12
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#define SDRAM_RES2 13
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#define SDRAM_RES3 14
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#define SDRAM_RES4 19
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#define SDRAM_RIP 31
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#define GET_SDRAM_MUX(x) ( \
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(GET_REG_BIT(x,SDRAM_MUX1)<<1)| \
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(GET_REG_BIT(x,SDRAM_MUX0)))
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/* System Controller */
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/* 0 1 3 4 5 16 20 28 29 30 */
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#define SYSCNTR_FLAG 0
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#define SYSCNTR_IP 1
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#define SYSCNTR_BIND2 3
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#define SYSCNTR_BIND1 4
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#define SYSCNTR_BIND0 5
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#define SYSCNTR_PRM 16
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#define SYSCNTR_ICW 20
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#define SYSCNTR_ISB2 28
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#define SYSCNTR_ISB1 29
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#define SYSCNTR_ISB0 30
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#define GET_SYSCNTR_BOOTIND(x) ( \
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(GET_REG_BIT(x,SYSCNTR_BIND2)<<2) |\
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(GET_REG_BIT(x,SYSCNTR_BIND1)<<1) |\
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(GET_REG_BIT(x,SYSCNTR_BIND0)))
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#define SET_SYSCNTR_BOOTIND(x) ( \
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(SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_BIND2)) |\
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(SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_BIND1))| \
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(SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_BIND0)))
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#define GET_SYSCNTR_ISB(x) ( \
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(GET_REG_BIT(x,SYSCNTR_ISB2)<<2)| \
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(GET_REG_BIT(x,SYSCNTR_ISB1)<<1)| \
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(GET_REG_BIT(x,SYSCNTR_ISB0)))
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#define SET_SYSCNTR_ISB(x) ( \
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(SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_ISB2))| \
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(SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_ISB))| \
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(SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_ISB0)))
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/* SDRAM Controller REG 3*/
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/* 9 10 11 12 13 14 19 31 */
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#define SDRAM_RES5 9
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#define SDRAM_CFG1 10
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#define SDRAM_CFG2 11
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#define SDRAM_CFG3 12
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#define SDRAM_RES6 13
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#define SDRAM_CFG5 14
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#define SDRAM_CFG6 19
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#define SDRAM_RES7 31
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#define GET_SDRAM_CFG(x) ( \
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(GET_REG_BIT(x,SDRAM_CFG6)<<4) |\
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(GET_REG_BIT(x,SDRAM_CFG5)<<3) |\
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(GET_REG_BIT(x,SDRAM_CFG3)<<2) |\
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(GET_REG_BIT(x,SDRAM_CFG2)<<1) |\
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(GET_REG_BIT(x,SDRAM_CFG1)))
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/* System Controller */
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/* 0 1 3 4 5 16 20 28 29 30 */
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#define SYSCNTR_BDIS 0
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#define SYSCNTR_PCIM 1
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#define SYSCNTR_CFG0 3
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#define SYSCNTR_CFG1 4
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#define SYSCNTR_CFG2 5
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#define SYSCNTR_CFG3 16
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#define SYSCNTR_BOOTEN 20
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#define SYSCNTR_CPU_VPP 28
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#define SYSCNTR_FL_VPP 29
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#define SYSCNTR_FL_WP 30
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#define GET_SYSCNTR_CFG(x) ( \
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(GET_REG_BIT(x,SYSCNTR_CFG3)<<3)| \
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(GET_REG_BIT(x,SYSCNTR_CFG2)<<2)| \
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(GET_REG_BIT(x,SYSCNTR_CFG1)<<1)| \
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(GET_REG_BIT(x,SYSCNTR_CFG0)))
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/***************************************************************
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* MISC Defines
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***************************************************************/
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#define PCI_VENDOR_ID_MPL 0x18E6
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#define PCI_DEVICE_ID_PATI 0x00DA
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#if defined(CONFIG_MIP405)
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#define PATI_FIRMWARE_START_OFFSET 0x00300000
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#define PATI_ISO_STRING "MEV-10084-001"
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#endif
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#define PATI_ENDIAN_MODE 0x3E
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/*******************************************
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* PATI Mapping:
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* -------------
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* PCI Map:
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* -------
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* All addreses are mapped into the memory area
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* (IO Area on some areas may also be possible)
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* - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
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* - pci_space0_addr: configurable
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* - pci_space1_addr configurable
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*
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* Local Map:
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* ----------
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* Local addresses (Remap)
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* - SDRAM 0x06000000 Size 16MByte mask 0xff000000
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* - EPLD CFG 0x07000000 Size 512Bytes
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* - FLASH 0x03000000 Size up to 8MByte
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* - CPU 0x01000000 Size 4MByte (only accessable if special configured)
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*
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* Implemention:
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* -------------
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* To prevent using large resources reservation on the host following
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* PCI mapping is choosed:
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* - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
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* - pci_space0_addr: configured to the EPLD Config Area size 256Bytes
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* - pci_space1_addr: configured to the SDRAM Area size 1MBytes, this
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* space is used to switch between SDRAM, Flash and CPU
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*
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*/
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/* Attribute definitions */
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#define PATI_BUS_SIZE_8 0
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#define PATI_BUS_SIZE_16 1
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#define PATI_BUS_SIZE_32 3
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#define PATI_SPACE0_MASK (0xFEFFFE00) /* Mask Attributes */
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#define PATI_SPACE1_MASK (0x00000000) /* Mask Attributes */
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#define PATI_EXTRA_LONG_EEPROM 1
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#define SPACE0_TA_ENABLE (1<<6)
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#define SPACE1_TA_ENABLE (1<<6)
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/* Config Area */
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#define PATI_LOC_CFG_ADDR 0x07000000 /* Local Address */
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#define PATI_LOC_CFG_MASK 0xFFFFFF00 /* 256 Bytes */
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/* Attributes */
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#define PATI_LOC_CFG_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
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#define PATI_LOC_CFG_BURST 0 /* No Burst */
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#define PATI_LOC_CFG_NO_PREFETCH 1 /* No Prefetch */
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#define PATI_LOC_CFG_TA_ENABLE 1 /* Enable TA */
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#define PATI_LOC_CFG_SPACE0_ATTR ( \
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PATI_LOC_CFG_BUS_SIZE | \
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(PATI_LOC_CFG_TA_ENABLE << 6) | \
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(PATI_LOC_CFG_NO_PREFETCH << 8) | \
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(PATI_LOC_CFG_BURST << 24) | \
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(PATI_EXTRA_LONG_EEPROM << 25))
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/* should never be used */
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#define PATI_LOC_CFG_SPACE1_ATTR ( \
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PATI_LOC_CFG_BUS_SIZE | \
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(PATI_LOC_CFG_TA_ENABLE << 6) | \
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(PATI_LOC_CFG_NO_PREFETCH << 9) | \
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(PATI_LOC_CFG_BURST << 8))
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/* SDRAM Area */
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#define PATI_LOC_SDRAM_ADDR 0x06000000 /* Local Address */
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#define PATI_LOC_SDRAM_MASK 0xFFF00000 /* 1MByte */
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/* Attributes */
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#define PATI_LOC_SDRAM_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
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#define PATI_LOC_SDRAM_BURST 0 /* No Burst */
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#define PATI_LOC_SDRAM_NO_PREFETCH 0 /* Prefetch */
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#define PATI_LOC_SDRAM_TA_ENABLE 1 /* Enable TA */
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/* should never be used */
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#define PATI_LOC_SDRAM_SPACE0_ATTR ( \
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PATI_LOC_SDRAM_BUS_SIZE | \
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(PATI_LOC_SDRAM_TA_ENABLE << 6) | \
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(PATI_LOC_SDRAM_NO_PREFETCH << 8) | \
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(PATI_LOC_SDRAM_BURST << 24) | \
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(PATI_EXTRA_LONG_EEPROM << 25))
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#define PATI_LOC_SDRAM_SPACE1_ATTR ( \
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PATI_LOC_SDRAM_BUS_SIZE | \
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(PATI_LOC_SDRAM_TA_ENABLE << 6) | \
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(PATI_LOC_SDRAM_NO_PREFETCH << 9) | \
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(PATI_LOC_SDRAM_BURST << 8))
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/* Flash Area */
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#define PATI_LOC_FLASH_ADDR 0x03000000 /* Local Address */
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#define PATI_LOC_FLASH_MASK 0xFFF00000 /* 1MByte */
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/* Attributes */
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#define PATI_LOC_FLASH_BUS_SIZE PATI_BUS_SIZE_16 /* 16 Bit */
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#define PATI_LOC_FLASH_BURST 0 /* No Burst */
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#define PATI_LOC_FLASH_NO_PREFETCH 1 /* No Prefetch */
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#define PATI_LOC_FLASH_TA_ENABLE 1 /* Enable TA */
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/* should never be used */
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#define PATI_LOC_FLASH_SPACE0_ATTR ( \
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PATI_LOC_FLASH_BUS_SIZE | \
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(PATI_LOC_FLASH_TA_ENABLE << 6) | \
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(PATI_LOC_FLASH_NO_PREFETCH << 8) | \
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(PATI_LOC_FLASH_BURST << 24) | \
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(PATI_EXTRA_LONG_EEPROM << 25))
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#define PATI_LOC_FLASH_SPACE1_ATTR ( \
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PATI_LOC_FLASH_BUS_SIZE | \
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(PATI_LOC_FLASH_TA_ENABLE << 6) | \
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(PATI_LOC_FLASH_NO_PREFETCH << 9) | \
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(PATI_LOC_FLASH_BURST << 8))
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/* CPU Area */
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#define PATI_LOC_CPU_ADDR 0x01000000 /* Local Address */
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#define PATI_LOC_CPU_MASK 0xFFF00000 /* 1Mbyte */
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/* Attributes */
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#define PATI_LOC_CPU_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
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#define PATI_LOC_CPU_BURST 0 /* No Burst */
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#define PATI_LOC_CPU_NO_PREFETCH 1 /* No Prefetch */
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#define PATI_LOC_CPU_TA_ENABLE 1 /* Enable TA */
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/* should never be used */
|
||
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#define PATI_LOC_CPU_SPACE0_ATTR ( \
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PATI_LOC_CPU_BUS_SIZE | \
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(PATI_LOC_CPU_TA_ENABLE << 6) | \
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(PATI_LOC_CPU_NO_PREFETCH << 8) | \
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(PATI_LOC_CPU_BURST << 24) | \
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||
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(PATI_EXTRA_CPU_EEPROM << 25))
|
||
|
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|
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#define PATI_LOC_CPU_SPACE1_ATTR ( \
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PATI_LOC_CPU_BUS_SIZE | \
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(PATI_LOC_CPU_TA_ENABLE << 6) | \
|
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(PATI_LOC_CPU_NO_PREFETCH << 9) | \
|
||
|
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(PATI_LOC_CPU_BURST << 8))
|
||
|
|
|
||
|
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/***************************************************
|
||
|
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* Hardware Config word definition
|
||
|
|
***************************************************/
|
||
|
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#define BOOT_EXT_FLASH 0x00000000
|
||
|
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#define BOOT_INT_FLASH 0x00000004
|
||
|
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#define BOOT_FROM_PCI 0x00000006
|
||
|
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#define BOOT_FROM_SDRAM 0x00000005
|
||
|
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|
||
|
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#define ENABLE_INT_ARB 0x00000008
|
||
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|
||
|
|
#define INITIAL_IRQ_PREF 0x00000010
|
||
|
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|
||
|
|
#define INITIAL_MEM_0M 0x00000000
|
||
|
|
#define INITIAL_MEM_4M 0x00000080
|
||
|
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#define INITIAL_MEM_8M 0x00000040
|
||
|
|
#define INITIAL_MEM_12M 0x000000C0
|
||
|
|
#define INITIAL_MEM_16M 0x00000020
|
||
|
|
#define INITIAL_MEM_20M 0x000000A0
|
||
|
|
#define INITIAL_MEM_24M 0x00000060
|
||
|
|
#define INITIAL_MEM_28M 0x000000E0
|
||
|
|
/* CONF */
|
||
|
|
#define INTERNAL_HWCONF 0x00000100
|
||
|
|
/* PRPM */
|
||
|
|
#define LOCAL_CPU_SLAVE 0x00000200
|
||
|
|
/* BDIS */
|
||
|
|
#define DISABLE_MEM_CNTR 0x00000400
|
||
|
|
/* PCIM */
|
||
|
|
#define PCI_MASTER_ONLY 0x00000800
|
||
|
|
|
||
|
|
|
||
|
|
#define PATI_HW_START ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF))
|
||
|
|
#define PATI_HW_PCI_ONLY ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
|
||
|
|
#define PATI_HW_CPU_ACC ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
|
||
|
|
#define PATI_HW_CPU_SLAVE ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE))
|
||
|
|
|
||
|
|
/***************************************************
|
||
|
|
* Direct Master Config
|
||
|
|
***************************************************/
|
||
|
|
#define PATI_DMASTER_PCI_ADDR 0x01000000
|
||
|
|
#define PATI_BUS_MASTER 1
|
||
|
|
|
||
|
|
|
||
|
|
#define PATI_DMASTER_MASK 0xFFF00000 /* 1MByte */
|
||
|
|
#define PATI_DMASTER_ADDR 0x01000000 /* Local Address */
|
||
|
|
|
||
|
|
#define PATI_DMASTER_MEMORY_EN 0x00000001 /* 0x00000001 */
|
||
|
|
#define PATI_DMASTER_READ_AHEAD 0x00000004 /* 0x00000004 */
|
||
|
|
#define PATI_DMASTER_READ_NOT_AHEAD 0x00000000 /* 0x00000004 */
|
||
|
|
#define PATI_DMASTER_PRE_SIZE_CNTRL_0 0x00000000
|
||
|
|
#define PATI_DMASTER_PRE_SIZE_CNTRL_4 0x00000008
|
||
|
|
#define PATI_DMASTER_PRE_SIZE_CNTRL_8 0x00001000
|
||
|
|
#define PATI_DMASTER_PRE_SIZE_CNTRL_16 0x00001008
|
||
|
|
#define PATI_DMASTER_REL_PCI 0x00000000
|
||
|
|
#define PATI_DMASTER_NOT_REL_PCI 0x00000010
|
||
|
|
#define PATI_DMASTER_WR_INVAL 0x00000200
|
||
|
|
#define PATI_DMASTER_NOT_WR_INVAL 0x00000000
|
||
|
|
#define PATI_DMASTER_PRE_LIMIT 0x00000800
|
||
|
|
#define PATI_DMASTER_PRE_CONT 0x00000000
|
||
|
|
#define PATI_DMASTER_DELAY_WR_0 0x00000000
|
||
|
|
#define PATI_DMASTER_DELAY_WR_4 0x00004000
|
||
|
|
#define PATI_DMASTER_DELAY_WR_8 0x00008000
|
||
|
|
#define PATI_DMASTER_DELAY_WR_16 0x0000C000
|
||
|
|
|
||
|
|
#define PATI_DMASTER_PCI_ADDR_MASK 0xFFFF0000
|
||
|
|
|
||
|
|
#define PATI_DMASTER_ATTR \
|
||
|
|
PATI_DMASTER_MEMORY_EN | \
|
||
|
|
PATI_DMASTER_READ_AHEAD | \
|
||
|
|
PATI_DMASTER_PRE_SIZE_CNTRL_4 | \
|
||
|
|
PATI_DMASTER_REL_PCI | \
|
||
|
|
PATI_DMASTER_NOT_WR_INVAL | \
|
||
|
|
PATI_DMASTER_PRE_LIMIT | \
|
||
|
|
PATI_DMASTER_DELAY_WR_0
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* #ifndef __PATI_H_ */
|