upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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122 lines
2.7 KiB
122 lines
2.7 KiB
21 years ago
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* 2004 (c) MontaVista Software, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <SA-1100.h>
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/* ------------------------------------------------------------------------- */
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/*
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* Board dependent initialisation
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*/
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#define ECOR 0x8000
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#define ECOR_RESET 0x80
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#define ECOR_LEVEL_IRQ 0x40
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#define ECOR_WR_ATTRIB 0x04
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#define ECOR_ENABLE 0x01
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#define ECSR 0x8002
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#define ECSR_IOIS8 0x20
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#define ECSR_PWRDWN 0x04
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#define ECSR_INT 0x02
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#define SMC_IO_SHIFT 2
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#define NCR_0 (*((volatile u_char *)(0x100000a0)))
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#define NCR_ENET_OSC_EN (1<<3)
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static inline u8
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readb(volatile u8 * p)
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{
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return *p;
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}
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static inline void
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writeb(u8 v, volatile u8 * p)
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{
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*p = v;
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}
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static void
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smc_init(void)
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{
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u8 ecor;
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u8 ecsr;
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volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25));
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NCR_0 |= NCR_ENET_OSC_EN;
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udelay(100);
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ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
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writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
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udelay(100);
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/*
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* The device will ignore all writes to the enable bit while
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* reset is asserted, even if the reset bit is cleared in the
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* same write. Must clear reset first, then enable the device.
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*/
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writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
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writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
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/*
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* Set the appropriate byte/word mode.
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*/
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ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
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ecsr |= ECSR_IOIS8;
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writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
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udelay(100);
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}
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static void
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neponset_init(void)
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{
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smc_init();
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}
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int
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board_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gd->bd->bi_arch_number = 25; /* Intel Assabet Board */
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gd->bd->bi_boot_params = 0xc0000100;
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neponset_init();
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return 0;
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}
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int
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dram_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return (0);
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}
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