upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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87 lines
2.7 KiB
87 lines
2.7 KiB
13 years ago
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/*
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* Copyright (C) 2011
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _DV_PSC_DEFS_H_
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#define _DV_PSC_DEFS_H_
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/*
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* Power/Sleep Ctrl Register structure
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* See sprufb3.pdf, Chapter 7
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*/
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struct dv_psc_regs {
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unsigned int pid; /* 0x000 */
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unsigned char rsvd0[16]; /* 0x004 */
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unsigned char rsvd1[4]; /* 0x014 */
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unsigned int inteval; /* 0x018 */
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unsigned char rsvd2[36]; /* 0x01C */
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unsigned int merrpr0; /* 0x040 */
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unsigned int merrpr1; /* 0x044 */
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unsigned char rsvd3[8]; /* 0x048 */
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unsigned int merrcr0; /* 0x050 */
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unsigned int merrcr1; /* 0x054 */
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unsigned char rsvd4[8]; /* 0x058 */
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unsigned int perrpr; /* 0x060 */
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unsigned char rsvd5[4]; /* 0x064 */
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unsigned int perrcr; /* 0x068 */
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unsigned char rsvd6[4]; /* 0x06C */
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unsigned int epcpr; /* 0x070 */
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unsigned char rsvd7[4]; /* 0x074 */
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unsigned int epccr; /* 0x078 */
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unsigned char rsvd8[144]; /* 0x07C */
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unsigned char rsvd9[20]; /* 0x10C */
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unsigned int ptcmd; /* 0x120 */
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unsigned char rsvd10[4]; /* 0x124 */
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unsigned int ptstat; /* 0x128 */
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unsigned char rsvd11[212]; /* 0x12C */
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unsigned int pdstat0; /* 0x200 */
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unsigned int pdstat1; /* 0x204 */
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unsigned char rsvd12[248]; /* 0x208 */
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unsigned int pdctl0; /* 0x300 */
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unsigned int pdctl1; /* 0x304 */
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unsigned char rsvd13[536]; /* 0x308 */
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unsigned int mckout0; /* 0x520 */
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unsigned int mckout1; /* 0x524 */
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unsigned char rsvd14[728]; /* 0x528 */
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unsigned int mdstat[52]; /* 0x800 */
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unsigned char rsvd15[304]; /* 0x8D0 */
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unsigned int mdctl[52]; /* 0xA00 */
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};
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/* PSC constants */
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#define EMURSTIE_MASK (0x00000200)
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#define PD0 (0)
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#define PSC_ENABLE (0x3)
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#define PSC_DISABLE (0x2)
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#define PSC_SYNCRESET (0x1)
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#define PSC_SWRSTDISABLE (0x0)
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#define PSC_GOSTAT (1 << 0)
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#define PSC_MD_STATE_MSK (0x1f)
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#define PSC_CMD_GO (1 << 0)
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#define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE)
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#endif /* _DV_PSC_DEFS_H_ */
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