upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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78 lines
3.0 KiB
78 lines
3.0 KiB
13 years ago
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#ifndef __SDMA_H
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#define __SDMA_H
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/* Copyright (C) 2011
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* Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* Functions */
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void omap3_dma_init(void);
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int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
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uint32_t sze);
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int omap3_dma_start_transfer(uint32_t chan);
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int omap3_dma_wait_for_transfer(uint32_t chan);
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int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config);
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int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config);
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/* Register settings */
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#define CSDP_DATA_TYPE_8BIT 0x0
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#define CSDP_DATA_TYPE_16BIT 0x1
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#define CSDP_DATA_TYPE_32BIT 0x2
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#define CSDP_SRC_BURST_SINGLE (0x0 << 7)
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#define CSDP_SRC_BURST_EN_16BYTES (0x1 << 7)
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#define CSDP_SRC_BURST_EN_32BYTES (0x2 << 7)
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#define CSDP_SRC_BURST_EN_64BYTES (0x3 << 7)
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#define CSDP_DST_BURST_SINGLE (0x0 << 14)
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#define CSDP_DST_BURST_EN_16BYTES (0x1 << 14)
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#define CSDP_DST_BURST_EN_32BYTES (0x2 << 14)
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#define CSDP_DST_BURST_EN_64BYTES (0x3 << 14)
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#define CSDP_DST_ENDIAN_LOCK_ADAPT (0x0 << 18)
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#define CSDP_DST_ENDIAN_LOCK_LOCK (0x1 << 18)
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#define CSDP_DST_ENDIAN_LITTLE (0x0 << 19)
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#define CSDP_DST_ENDIAN_BIG (0x1 << 19)
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#define CSDP_SRC_ENDIAN_LOCK_ADAPT (0x0 << 20)
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#define CSDP_SRC_ENDIAN_LOCK_LOCK (0x1 << 20)
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#define CSDP_SRC_ENDIAN_LITTLE (0x0 << 21)
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#define CSDP_SRC_ENDIAN_BIG (0x1 << 21)
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#define CCR_READ_PRIORITY_LOW (0x0 << 6)
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#define CCR_READ_PRIORITY_HIGH (0x1 << 6)
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#define CCR_ENABLE_DISABLED (0x0 << 7)
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#define CCR_ENABLE_ENABLE (0x1 << 7)
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#define CCR_SRC_AMODE_CONSTANT (0x0 << 12)
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#define CCR_SRC_AMODE_POST_INC (0x1 << 12)
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#define CCR_SRC_AMODE_SINGLE_IDX (0x2 << 12)
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#define CCR_SRC_AMODE_DOUBLE_IDX (0x3 << 12)
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#define CCR_DST_AMODE_CONSTANT (0x0 << 14)
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#define CCR_DST_AMODE_POST_INC (0x1 << 14)
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#define CCR_DST_AMODE_SINGLE_IDX (0x2 << 14)
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#define CCR_DST_AMODE_SOUBLE_IDX (0x3 << 14)
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#define CCR_RD_ACTIVE_MASK (1 << 9)
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#define CCR_WR_ACTIVE_MASK (1 << 10)
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#define CSR_TRANS_ERR (1 << 8)
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#define CSR_SUPERVISOR_ERR (1 << 10)
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#define CSR_MISALIGNED_ADRS_ERR (1 << 11)
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/* others */
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#define CHAN_NR_MIN 0
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#define CHAN_NR_MAX 31
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#endif /* __SDMA_H */
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