upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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664 lines
18 KiB
664 lines
18 KiB
22 years ago
|
/*
|
||
|
* (C) Copyright 2002
|
||
|
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
|
||
|
*
|
||
|
* See file CREDITS for list of people who contributed to this
|
||
|
* project.
|
||
|
*
|
||
|
* This program is free software; you can redistribute it and/or
|
||
|
* modify it under the terms of the GNU General Public License as
|
||
|
* published by the Free Software Foundation; either version 2 of
|
||
|
* the License, or (at your option) any later version.
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||
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*
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||
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* This program is distributed in the hope that it will be useful,
|
||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||
|
* GNU General Public License for more details.
|
||
|
*
|
||
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* You should have received a copy of the GNU General Public License
|
||
|
* along with this program; if not, write to the Free Software
|
||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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||
|
*
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||
|
*/
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||
|
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||
|
#include <common.h> /* core U-Boot definitions */
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||
|
#include <spartan2.h> /* Spartan-II device family */
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||
|
|
||
|
/* Define FPGA_DEBUG to get debug printf's */
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|
#ifdef FPGA_DEBUG
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||
|
#define PRINTF(fmt,args...) printf (fmt ,##args)
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|
#else
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|
#define PRINTF(fmt,args...)
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|
#endif
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|
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16 years ago
|
#undef CONFIG_SYS_FPGA_CHECK_BUSY
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#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
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22 years ago
|
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||
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/* Note: The assumption is that we cannot possibly run fast enough to
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|
* overrun the device (the Slave Parallel mode can free run at 50MHz).
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|
* If there is a need to operate slower, define CONFIG_FPGA_DELAY in
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|
* the board config file to slow things down.
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|
*/
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|
#ifndef CONFIG_FPGA_DELAY
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|
#define CONFIG_FPGA_DELAY()
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|
#endif
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|
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16 years ago
|
#ifndef CONFIG_SYS_FPGA_WAIT
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#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
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22 years ago
|
#endif
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|
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static int Spartan2_sp_load( Xilinx_desc *desc, void *buf, size_t bsize );
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|
static int Spartan2_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize );
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|
/* static int Spartan2_sp_info( Xilinx_desc *desc ); */
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|
static int Spartan2_sp_reloc( Xilinx_desc *desc, ulong reloc_offset );
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|
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|
static int Spartan2_ss_load( Xilinx_desc *desc, void *buf, size_t bsize );
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|
static int Spartan2_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize );
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|
/* static int Spartan2_ss_info( Xilinx_desc *desc ); */
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static int Spartan2_ss_reloc( Xilinx_desc *desc, ulong reloc_offset );
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|
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/* ------------------------------------------------------------------------- */
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/* Spartan-II Generic Implementation */
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int Spartan2_load (Xilinx_desc * desc, void *buf, size_t bsize)
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|
{
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int ret_val = FPGA_FAIL;
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|
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switch (desc->iface) {
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case slave_serial:
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PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
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ret_val = Spartan2_ss_load (desc, buf, bsize);
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break;
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|
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case slave_parallel:
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PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
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ret_val = Spartan2_sp_load (desc, buf, bsize);
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|
break;
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|
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|
default:
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printf ("%s: Unsupported interface type, %d\n",
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|
__FUNCTION__, desc->iface);
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}
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|
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return ret_val;
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}
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|
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int Spartan2_dump (Xilinx_desc * desc, void *buf, size_t bsize)
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|
{
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int ret_val = FPGA_FAIL;
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switch (desc->iface) {
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|
case slave_serial:
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PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
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ret_val = Spartan2_ss_dump (desc, buf, bsize);
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|
break;
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|
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case slave_parallel:
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PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
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ret_val = Spartan2_sp_dump (desc, buf, bsize);
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break;
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|
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default:
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printf ("%s: Unsupported interface type, %d\n",
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__FUNCTION__, desc->iface);
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}
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return ret_val;
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}
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|
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int Spartan2_info( Xilinx_desc *desc )
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|
{
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return FPGA_SUCCESS;
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}
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|
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|
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int Spartan2_reloc (Xilinx_desc * desc, ulong reloc_offset)
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|
{
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int ret_val = FPGA_FAIL; /* assume a failure */
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|
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if (desc->family != Xilinx_Spartan2) {
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printf ("%s: Unsupported family type, %d\n",
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__FUNCTION__, desc->family);
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return FPGA_FAIL;
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} else
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switch (desc->iface) {
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case slave_serial:
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|
ret_val = Spartan2_ss_reloc (desc, reloc_offset);
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break;
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|
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case slave_parallel:
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ret_val = Spartan2_sp_reloc (desc, reloc_offset);
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break;
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default:
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printf ("%s: Unsupported interface type, %d\n",
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__FUNCTION__, desc->iface);
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}
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return ret_val;
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}
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/* ------------------------------------------------------------------------- */
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/* Spartan-II Slave Parallel Generic Implementation */
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|
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static int Spartan2_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
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|
{
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int ret_val = FPGA_FAIL; /* assume the worst */
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Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
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|
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PRINTF ("%s: start with interface functions @ 0x%p\n",
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__FUNCTION__, fn);
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if (fn) {
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size_t bytecount = 0;
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unsigned char *data = (unsigned char *) buf;
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int cookie = desc->cookie; /* make a local copy */
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unsigned long ts; /* timestamp */
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|
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PRINTF ("%s: Function Table:\n"
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"ptr:\t0x%p\n"
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"struct: 0x%p\n"
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"pre: 0x%p\n"
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"pgm:\t0x%p\n"
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"init:\t0x%p\n"
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"err:\t0x%p\n"
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"clk:\t0x%p\n"
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|
"cs:\t0x%p\n"
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|
"wr:\t0x%p\n"
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|
"read data:\t0x%p\n"
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|
"write data:\t0x%p\n"
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|
"busy:\t0x%p\n"
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|
"abort:\t0x%p\n",
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|
"post:\t0x%p\n\n",
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|
__FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
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|
fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
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fn->abort, fn->post);
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|
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|
/*
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|
* This code is designed to emulate the "Express Style"
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* Continuous Data Loading in Slave Parallel Mode for
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* the Spartan-II Family.
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*/
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16 years ago
|
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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22 years ago
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printf ("Loading FPGA Device %d...\n", cookie);
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#endif
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/*
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* Run the pre configuration function if there is one.
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*/
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if (*fn->pre) {
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(*fn->pre) (cookie);
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}
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|
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/* Establish the initial state */
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(*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
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|
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||
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/* Get ready for the burn */
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CONFIG_FPGA_DELAY ();
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(*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
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|
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ts = get_timer (0); /* get current time */
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/* Now wait for INIT and BUSY to go high */
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do {
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CONFIG_FPGA_DELAY ();
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16 years ago
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if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
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22 years ago
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puts ("** Timeout waiting for INIT to clear.\n");
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(*fn->abort) (cookie); /* abort the burn */
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return FPGA_FAIL;
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}
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} while ((*fn->init) (cookie) && (*fn->busy) (cookie));
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|
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(*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */
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(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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|
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||
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/* Load the data */
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while (bytecount < bsize) {
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/* XXX - do we check for an Ctrl-C press in here ??? */
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/* XXX - Check the error bit? */
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|
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||
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(*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */
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|
CONFIG_FPGA_DELAY ();
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(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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|
|
||
16 years ago
|
#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
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22 years ago
|
ts = get_timer (0); /* get current time */
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|
while ((*fn->busy) (cookie)) {
|
||
|
/* XXX - we should have a check in here somewhere to
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||
|
* make sure we aren't busy forever... */
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||
|
|
||
|
CONFIG_FPGA_DELAY ();
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||
|
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
|
||
|
CONFIG_FPGA_DELAY ();
|
||
|
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
|
||
|
|
||
16 years ago
|
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
|
||
22 years ago
|
puts ("** Timeout waiting for BUSY to clear.\n");
|
||
|
(*fn->abort) (cookie); /* abort the burn */
|
||
|
return FPGA_FAIL;
|
||
|
}
|
||
|
}
|
||
|
#endif
|
||
|
|
||
16 years ago
|
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
|
||
22 years ago
|
if (bytecount % (bsize / 40) == 0)
|
||
|
putc ('.'); /* let them know we are alive */
|
||
|
#endif
|
||
|
}
|
||
|
|
||
|
CONFIG_FPGA_DELAY ();
|
||
|
(*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */
|
||
|
(*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */
|
||
|
|
||
16 years ago
|
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
|
||
22 years ago
|
putc ('\n'); /* terminate the dotted line */
|
||
|
#endif
|
||
|
|
||
|
/* now check for done signal */
|
||
|
ts = get_timer (0); /* get current time */
|
||
|
ret_val = FPGA_SUCCESS;
|
||
|
while ((*fn->done) (cookie) == FPGA_FAIL) {
|
||
|
/* XXX - we should have a check in here somewhere to
|
||
|
* make sure we aren't busy forever... */
|
||
|
|
||
|
CONFIG_FPGA_DELAY ();
|
||
|
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
|
||
|
CONFIG_FPGA_DELAY ();
|
||
|
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
|
||
|
|
||
16 years ago
|
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
|
||
22 years ago
|
puts ("** Timeout waiting for DONE to clear.\n");
|
||
|
(*fn->abort) (cookie); /* abort the burn */
|
||
|
ret_val = FPGA_FAIL;
|
||
|
break;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
if (ret_val == FPGA_SUCCESS) {
|
||
16 years ago
|
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
|
||
22 years ago
|
puts ("Done.\n");
|
||
|
#endif
|
||
|
}
|
||
|
/*
|
||
|
* Run the post configuration function if there is one.
|
||
|
*/
|
||
|
if (*fn->post) {
|
||
|
(*fn->post) (cookie);
|
||
|
}
|
||
|
|
||
|
else {
|
||
16 years ago
|
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
|
||
22 years ago
|
puts ("Fail.\n");
|
||
|
#endif
|
||
|
}
|
||
|
|
||
|
} else {
|
||
|
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
|
||
|
}
|
||
|
|
||
|
return ret_val;
|
||
|
}
|
||
|
|
||
|
static int Spartan2_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize)
|
||
|
{
|
||
|
int ret_val = FPGA_FAIL; /* assume the worst */
|
||
|
Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
|
||
|
|
||
|
if (fn) {
|
||
|
unsigned char *data = (unsigned char *) buf;
|
||
|
size_t bytecount = 0;
|
||
|
int cookie = desc->cookie; /* make a local copy */
|
||
|
|
||
|
printf ("Starting Dump of FPGA Device %d...\n", cookie);
|
||
|
|
||
|
(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
|
||
|
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
|
||
|
|
||
|
/* dump the data */
|
||
|
while (bytecount < bsize) {
|
||
|
/* XXX - do we check for an Ctrl-C press in here ??? */
|
||
|
|
||
|
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
|
||
|
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
|
||
|
(*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */
|
||
16 years ago
|
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
|
||
22 years ago
|
if (bytecount % (bsize / 40) == 0)
|
||
|
putc ('.'); /* let them know we are alive */
|
||
|
#endif
|
||
|
}
|
||
|
|
||
|
(*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */
|
||
|
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
|
||
|
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
|
||
|
|
||
16 years ago
|
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
|
||
22 years ago
|
putc ('\n'); /* terminate the dotted line */
|
||
|
#endif
|
||
|
puts ("Done.\n");
|
||
|
|
||
|
/* XXX - checksum the data? */
|
||
|
} else {
|
||
|
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
|
||
|
}
|
||
|
|
||
|
return ret_val;
|
||
|
}
|
||
|
|
||
|
|
||
|
static int Spartan2_sp_reloc (Xilinx_desc * desc, ulong reloc_offset)
|
||
|
{
|
||
|
int ret_val = FPGA_FAIL; /* assume the worst */
|
||
|
Xilinx_Spartan2_Slave_Parallel_fns *fn_r, *fn =
|
||
|
(Xilinx_Spartan2_Slave_Parallel_fns *) (desc->iface_fns);
|
||
|
|
||
|
if (fn) {
|
||
|
ulong addr;
|
||
|
|
||
|
/* Get the relocated table address */
|
||
|
addr = (ulong) fn + reloc_offset;
|
||
|
fn_r = (Xilinx_Spartan2_Slave_Parallel_fns *) addr;
|
||
|
|
||
|
if (!fn_r->relocated) {
|
||
|
|
||
|
if (memcmp (fn_r, fn,
|
||
|
sizeof (Xilinx_Spartan2_Slave_Parallel_fns))
|
||
|
== 0) {
|
||
|
/* good copy of the table, fix the descriptor pointer */
|
||
|
desc->iface_fns = fn_r;
|
||
|
} else {
|
||
|
PRINTF ("%s: Invalid function table at 0x%p\n",
|
||
|
__FUNCTION__, fn_r);
|
||
|
return FPGA_FAIL;
|
||
|
}
|
||
|
|
||
|
PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
|
||
|
desc);
|
||
|
|
||
|
addr = (ulong) (fn->pre) + reloc_offset;
|
||
|
fn_r->pre = (Xilinx_pre_fn) addr;
|
||
|
|
||
|
addr = (ulong) (fn->pgm) + reloc_offset;
|
||
|
fn_r->pgm = (Xilinx_pgm_fn) addr;
|
||
|
|
||
|
addr = (ulong) (fn->init) + reloc_offset;
|
||
|
fn_r->init = (Xilinx_init_fn) addr;
|
||
|
|
||
|
addr = (ulong) (fn->done) + reloc_offset;
|
||
|
fn_r->done = (Xilinx_done_fn) addr;
|
||
|
|
||
|
addr = (ulong) (fn->clk) + reloc_offset;
|
||
|
fn_r->clk = (Xilinx_clk_fn) addr;
|
||
|
|
||
|
addr = (ulong) (fn->err) + reloc_offset;
|
||
|
fn_r->err = (Xilinx_err_fn) addr;
|
||
|
|
||
|
addr = (ulong) (fn->cs) + reloc_offset;
|
||
|
fn_r->cs = (Xilinx_cs_fn) addr;
|
||
|
|
||
|
addr = (ulong) (fn->wr) + reloc_offset;
|
||
|
fn_r->wr = (Xilinx_wr_fn) addr;
|
||
|
|
||
|
addr = (ulong) (fn->rdata) + reloc_offset;
|
||
|
fn_r->rdata = (Xilinx_rdata_fn) addr;
|
||
|
|
||
|
addr = (ulong) (fn->wdata) + reloc_offset;
|
||
|
fn_r->wdata = (Xilinx_wdata_fn) addr;
|
||
|
|
||
|
addr = (ulong) (fn->busy) + reloc_offset;
|
||
|
fn_r->busy = (Xilinx_busy_fn) addr;
|
||
|
|
||
|
addr = (ulong) (fn->abort) + reloc_offset;
|
||
|
fn_r->abort = (Xilinx_abort_fn) addr;
|
||
|
|
||
|
addr = (ulong) (fn->post) + reloc_offset;
|
||
|
fn_r->post = (Xilinx_post_fn) addr;
|
||
|
|
||
|
fn_r->relocated = TRUE;
|
||
|
|
||
|
} else {
|
||
|
/* this table has already been moved */
|
||
|
/* XXX - should check to see if the descriptor is correct */
|
||
|
desc->iface_fns = fn_r;
|
||
|
}
|
||
|
|
||
|
ret_val = FPGA_SUCCESS;
|
||
|
} else {
|
||
|
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
|
||
|
}
|
||
|
|
||
|
return ret_val;
|
||
|
|
||
|
}
|
||
|
|
||
|
/* ------------------------------------------------------------------------- */
|
||
|
|
||
|
static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
|
||
|
{
|
||
22 years ago
|
int ret_val = FPGA_FAIL; /* assume the worst */
|
||
22 years ago
|
Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns;
|
||
22 years ago
|
int i;
|
||
17 years ago
|
unsigned char val;
|
||
22 years ago
|
|
||
22 years ago
|
PRINTF ("%s: start with interface functions @ 0x%p\n",
|
||
|
__FUNCTION__, fn);
|
||
|
|
||
|
if (fn) {
|
||
|
size_t bytecount = 0;
|
||
|
unsigned char *data = (unsigned char *) buf;
|
||
|
int cookie = desc->cookie; /* make a local copy */
|
||
|
unsigned long ts; /* timestamp */
|
||
|
|
||
|
PRINTF ("%s: Function Table:\n"
|
||
|
"ptr:\t0x%p\n"
|
||
|
"struct: 0x%p\n"
|
||
|
"pgm:\t0x%p\n"
|
||
|
"init:\t0x%p\n"
|
||
|
"clk:\t0x%p\n"
|
||
|
"wr:\t0x%p\n"
|
||
|
"done:\t0x%p\n\n",
|
||
22 years ago
|
__FUNCTION__, &fn, fn, fn->pgm, fn->init,
|
||
|
fn->clk, fn->wr, fn->done);
|
||
16 years ago
|
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
|
||
22 years ago
|
printf ("Loading FPGA Device %d...\n", cookie);
|
||
|
#endif
|
||
|
|
||
|
/*
|
||
|
* Run the pre configuration function if there is one.
|
||
|
*/
|
||
|
if (*fn->pre) {
|
||
|
(*fn->pre) (cookie);
|
||
|
}
|
||
|
|
||
|
/* Establish the initial state */
|
||
|
(*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
|
||
|
|
||
22 years ago
|
/* Wait for INIT state (init low) */
|
||
22 years ago
|
ts = get_timer (0); /* get current time */
|
||
|
do {
|
||
|
CONFIG_FPGA_DELAY ();
|
||
16 years ago
|
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
|
||
22 years ago
|
puts ("** Timeout waiting for INIT to start.\n");
|
||
|
return FPGA_FAIL;
|
||
|
}
|
||
|
} while (!(*fn->init) (cookie));
|
||
22 years ago
|
|
||
22 years ago
|
/* Get ready for the burn */
|
||
|
CONFIG_FPGA_DELAY ();
|
||
|
(*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
|
||
|
|
||
|
ts = get_timer (0); /* get current time */
|
||
|
/* Now wait for INIT to go high */
|
||
|
do {
|
||
|
CONFIG_FPGA_DELAY ();
|
||
16 years ago
|
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
|
||
22 years ago
|
puts ("** Timeout waiting for INIT to clear.\n");
|
||
|
return FPGA_FAIL;
|
||
|
}
|
||
|
} while ((*fn->init) (cookie));
|
||
|
|
||
|
/* Load the data */
|
||
|
while (bytecount < bsize) {
|
||
22 years ago
|
|
||
|
/* Xilinx detects an error if INIT goes low (active)
|
||
|
while DONE is low (inactive) */
|
||
|
if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
|
||
|
puts ("** CRC error during FPGA load.\n");
|
||
|
return (FPGA_FAIL);
|
||
|
}
|
||
|
val = data [bytecount ++];
|
||
|
i = 8;
|
||
|
do {
|
||
|
/* Deassert the clock */
|
||
|
(*fn->clk) (FALSE, TRUE, cookie);
|
||
|
CONFIG_FPGA_DELAY ();
|
||
|
/* Write data */
|
||
17 years ago
|
(*fn->wr) ((val & 0x80), TRUE, cookie);
|
||
22 years ago
|
CONFIG_FPGA_DELAY ();
|
||
|
/* Assert the clock */
|
||
|
(*fn->clk) (TRUE, TRUE, cookie);
|
||
|
CONFIG_FPGA_DELAY ();
|
||
|
val <<= 1;
|
||
|
i --;
|
||
|
} while (i > 0);
|
||
|
|
||
16 years ago
|
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
|
||
22 years ago
|
if (bytecount % (bsize / 40) == 0)
|
||
|
putc ('.'); /* let them know we are alive */
|
||
|
#endif
|
||
|
}
|
||
|
|
||
|
CONFIG_FPGA_DELAY ();
|
||
|
|
||
16 years ago
|
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
|
||
22 years ago
|
putc ('\n'); /* terminate the dotted line */
|
||
|
#endif
|
||
|
|
||
|
/* now check for done signal */
|
||
|
ts = get_timer (0); /* get current time */
|
||
|
ret_val = FPGA_SUCCESS;
|
||
22 years ago
|
(*fn->wr) (TRUE, TRUE, cookie);
|
||
22 years ago
|
|
||
|
while (! (*fn->done) (cookie)) {
|
||
|
/* XXX - we should have a check in here somewhere to
|
||
|
* make sure we aren't busy forever... */
|
||
|
|
||
|
CONFIG_FPGA_DELAY ();
|
||
|
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
|
||
|
CONFIG_FPGA_DELAY ();
|
||
|
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
|
||
|
|
||
22 years ago
|
putc ('*');
|
||
|
|
||
16 years ago
|
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
|
||
22 years ago
|
puts ("** Timeout waiting for DONE to clear.\n");
|
||
|
ret_val = FPGA_FAIL;
|
||
|
break;
|
||
|
}
|
||
|
}
|
||
|
putc ('\n'); /* terminate the dotted line */
|
||
|
|
||
17 years ago
|
/*
|
||
|
* Run the post configuration function if there is one.
|
||
|
*/
|
||
|
if (*fn->post) {
|
||
|
(*fn->post) (cookie);
|
||
|
}
|
||
|
|
||
16 years ago
|
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
|
||
22 years ago
|
if (ret_val == FPGA_SUCCESS) {
|
||
|
puts ("Done.\n");
|
||
|
}
|
||
|
else {
|
||
|
puts ("Fail.\n");
|
||
|
}
|
||
|
#endif
|
||
|
|
||
|
} else {
|
||
|
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
|
||
|
}
|
||
|
|
||
|
return ret_val;
|
||
22 years ago
|
}
|
||
|
|
||
|
static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
|
||
|
{
|
||
22 years ago
|
/* Readback is only available through the Slave Parallel and */
|
||
|
/* boundary-scan interfaces. */
|
||
22 years ago
|
printf ("%s: Slave Serial Dumping is unavailable\n",
|
||
22 years ago
|
__FUNCTION__);
|
||
|
return FPGA_FAIL;
|
||
|
}
|
||
|
|
||
|
static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
|
||
|
{
|
||
|
int ret_val = FPGA_FAIL; /* assume the worst */
|
||
22 years ago
|
Xilinx_Spartan2_Slave_Serial_fns *fn_r, *fn =
|
||
22 years ago
|
(Xilinx_Spartan2_Slave_Serial_fns *) (desc->iface_fns);
|
||
|
|
||
|
if (fn) {
|
||
22 years ago
|
ulong addr;
|
||
|
|
||
|
/* Get the relocated table address */
|
||
|
addr = (ulong) fn + reloc_offset;
|
||
|
fn_r = (Xilinx_Spartan2_Slave_Serial_fns *) addr;
|
||
|
|
||
|
if (!fn_r->relocated) {
|
||
|
|
||
|
if (memcmp (fn_r, fn,
|
||
|
sizeof (Xilinx_Spartan2_Slave_Serial_fns))
|
||
|
== 0) {
|
||
|
/* good copy of the table, fix the descriptor pointer */
|
||
|
desc->iface_fns = fn_r;
|
||
|
} else {
|
||
|
PRINTF ("%s: Invalid function table at 0x%p\n",
|
||
|
__FUNCTION__, fn_r);
|
||
|
return FPGA_FAIL;
|
||
|
}
|
||
|
|
||
|
PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
|
||
|
desc);
|
||
|
|
||
17 years ago
|
if (fn->pre) {
|
||
|
addr = (ulong) (fn->pre) + reloc_offset;
|
||
|
fn_r->pre = (Xilinx_pre_fn) addr;
|
||
|
}
|
||
22 years ago
|
|
||
|
addr = (ulong) (fn->pgm) + reloc_offset;
|
||
|
fn_r->pgm = (Xilinx_pgm_fn) addr;
|
||
|
|
||
|
addr = (ulong) (fn->init) + reloc_offset;
|
||
|
fn_r->init = (Xilinx_init_fn) addr;
|
||
|
|
||
|
addr = (ulong) (fn->done) + reloc_offset;
|
||
|
fn_r->done = (Xilinx_done_fn) addr;
|
||
|
|
||
|
addr = (ulong) (fn->clk) + reloc_offset;
|
||
|
fn_r->clk = (Xilinx_clk_fn) addr;
|
||
|
|
||
|
addr = (ulong) (fn->wr) + reloc_offset;
|
||
|
fn_r->wr = (Xilinx_wr_fn) addr;
|
||
|
|
||
17 years ago
|
if (fn->post) {
|
||
|
addr = (ulong) (fn->post) + reloc_offset;
|
||
|
fn_r->post = (Xilinx_post_fn) addr;
|
||
|
}
|
||
|
|
||
22 years ago
|
fn_r->relocated = TRUE;
|
||
|
|
||
|
} else {
|
||
|
/* this table has already been moved */
|
||
|
/* XXX - should check to see if the descriptor is correct */
|
||
|
desc->iface_fns = fn_r;
|
||
|
}
|
||
|
|
||
|
ret_val = FPGA_SUCCESS;
|
||
22 years ago
|
} else {
|
||
|
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
|
||
|
}
|
||
|
|
||
|
return ret_val;
|
||
|
|
||
|
}
|