upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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220 lines
4.3 KiB
220 lines
4.3 KiB
9 years ago
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/*
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* Altera SoCFPGA PinMux configuration
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SOCFPGA_PINMUX_CONFIG_H__
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#define __SOCFPGA_PINMUX_CONFIG_H__
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const u8 sys_mgr_init_table[] = {
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0, /* EMACIO0 */
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2, /* EMACIO1 */
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2, /* EMACIO2 */
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2, /* EMACIO3 */
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2, /* EMACIO4 */
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2, /* EMACIO5 */
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2, /* EMACIO6 */
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2, /* EMACIO7 */
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2, /* EMACIO8 */
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0, /* EMACIO9 */
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2, /* EMACIO10 */
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2, /* EMACIO11 */
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2, /* EMACIO12 */
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2, /* EMACIO13 */
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0, /* EMACIO14 */
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0, /* EMACIO15 */
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0, /* EMACIO16 */
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0, /* EMACIO17 */
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0, /* EMACIO18 */
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0, /* EMACIO19 */
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3, /* FLASHIO0 */
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0, /* FLASHIO1 */
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3, /* FLASHIO2 */
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3, /* FLASHIO3 */
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0, /* FLASHIO4 */
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0, /* FLASHIO5 */
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0, /* FLASHIO6 */
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0, /* FLASHIO7 */
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0, /* FLASHIO8 */
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3, /* FLASHIO9 */
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3, /* FLASHIO10 */
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3, /* FLASHIO11 */
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0, /* GENERALIO0 */
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1, /* GENERALIO1 */
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1, /* GENERALIO2 */
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1, /* GENERALIO3 */
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1, /* GENERALIO4 */
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0, /* GENERALIO5 */
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0, /* GENERALIO6 */
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1, /* GENERALIO7 */
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1, /* GENERALIO8 */
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0, /* GENERALIO9 */
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0, /* GENERALIO10 */
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0, /* GENERALIO11 */
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0, /* GENERALIO12 */
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0, /* GENERALIO13 */
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0, /* GENERALIO14 */
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0, /* GENERALIO15 */
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0, /* GENERALIO16 */
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0, /* GENERALIO17 */
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0, /* GENERALIO18 */
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0, /* GENERALIO19 */
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0, /* GENERALIO20 */
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0, /* GENERALIO21 */
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0, /* GENERALIO22 */
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0, /* GENERALIO23 */
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0, /* GENERALIO24 */
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0, /* GENERALIO25 */
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0, /* GENERALIO26 */
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0, /* GENERALIO27 */
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0, /* GENERALIO28 */
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0, /* GENERALIO29 */
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0, /* GENERALIO30 */
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0, /* GENERALIO31 */
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2, /* MIXED1IO0 */
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2, /* MIXED1IO1 */
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2, /* MIXED1IO2 */
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2, /* MIXED1IO3 */
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2, /* MIXED1IO4 */
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2, /* MIXED1IO5 */
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2, /* MIXED1IO6 */
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2, /* MIXED1IO7 */
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2, /* MIXED1IO8 */
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2, /* MIXED1IO9 */
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2, /* MIXED1IO10 */
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2, /* MIXED1IO11 */
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2, /* MIXED1IO12 */
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2, /* MIXED1IO13 */
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0, /* MIXED1IO14 */
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3, /* MIXED1IO15 */
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3, /* MIXED1IO16 */
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3, /* MIXED1IO17 */
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3, /* MIXED1IO18 */
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3, /* MIXED1IO19 */
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3, /* MIXED1IO20 */
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0, /* MIXED1IO21 */
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0, /* MIXED2IO0 */
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0, /* MIXED2IO1 */
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0, /* MIXED2IO2 */
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0, /* MIXED2IO3 */
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0, /* MIXED2IO4 */
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0, /* MIXED2IO5 */
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0, /* MIXED2IO6 */
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0, /* MIXED2IO7 */
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0, /* GPLINMUX48 */
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0, /* GPLINMUX49 */
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0, /* GPLINMUX50 */
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0, /* GPLINMUX51 */
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0, /* GPLINMUX52 */
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0, /* GPLINMUX53 */
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0, /* GPLINMUX54 */
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0, /* GPLINMUX55 */
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0, /* GPLINMUX56 */
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0, /* GPLINMUX57 */
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0, /* GPLINMUX58 */
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0, /* GPLINMUX59 */
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0, /* GPLINMUX60 */
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0, /* GPLINMUX61 */
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0, /* GPLINMUX62 */
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0, /* GPLINMUX63 */
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0, /* GPLINMUX64 */
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0, /* GPLINMUX65 */
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0, /* GPLINMUX66 */
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0, /* GPLINMUX67 */
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0, /* GPLINMUX68 */
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0, /* GPLINMUX69 */
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0, /* GPLINMUX70 */
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0, /* GPLMUX0 */
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1, /* GPLMUX1 */
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1, /* GPLMUX2 */
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1, /* GPLMUX3 */
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1, /* GPLMUX4 */
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1, /* GPLMUX5 */
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1, /* GPLMUX6 */
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1, /* GPLMUX7 */
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1, /* GPLMUX8 */
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0, /* GPLMUX9 */
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1, /* GPLMUX10 */
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1, /* GPLMUX11 */
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1, /* GPLMUX12 */
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1, /* GPLMUX13 */
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1, /* GPLMUX14 */
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1, /* GPLMUX15 */
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1, /* GPLMUX16 */
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1, /* GPLMUX17 */
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1, /* GPLMUX18 */
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1, /* GPLMUX19 */
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1, /* GPLMUX20 */
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1, /* GPLMUX21 */
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1, /* GPLMUX22 */
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1, /* GPLMUX23 */
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1, /* GPLMUX24 */
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1, /* GPLMUX25 */
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1, /* GPLMUX26 */
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1, /* GPLMUX27 */
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0, /* GPLMUX28 */
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1, /* GPLMUX29 */
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1, /* GPLMUX30 */
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1, /* GPLMUX31 */
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1, /* GPLMUX32 */
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1, /* GPLMUX33 */
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1, /* GPLMUX34 */
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0, /* GPLMUX35 */
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1, /* GPLMUX36 */
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0, /* GPLMUX37 */
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1, /* GPLMUX38 */
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1, /* GPLMUX39 */
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0, /* GPLMUX40 */
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0, /* GPLMUX41 */
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0, /* GPLMUX42 */
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0, /* GPLMUX43 */
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0, /* GPLMUX44 */
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1, /* GPLMUX45 */
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1, /* GPLMUX46 */
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1, /* GPLMUX47 */
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0, /* GPLMUX48 */
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1, /* GPLMUX49 */
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1, /* GPLMUX50 */
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1, /* GPLMUX51 */
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1, /* GPLMUX52 */
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0, /* GPLMUX53 */
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0, /* GPLMUX54 */
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1, /* GPLMUX55 */
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1, /* GPLMUX56 */
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0, /* GPLMUX57 */
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0, /* GPLMUX58 */
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0, /* GPLMUX59 */
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0, /* GPLMUX60 */
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0, /* GPLMUX61 */
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0, /* GPLMUX62 */
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1, /* GPLMUX63 */
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1, /* GPLMUX64 */
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1, /* GPLMUX65 */
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1, /* GPLMUX66 */
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1, /* GPLMUX67 */
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1, /* GPLMUX68 */
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1, /* GPLMUX69 */
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1, /* GPLMUX70 */
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0, /* NANDUSEFPGA */
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0, /* UART0USEFPGA */
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0, /* RGMII1USEFPGA */
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0, /* SPIS0USEFPGA */
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0, /* CAN0USEFPGA */
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0, /* I2C0USEFPGA */
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0, /* SDMMCUSEFPGA */
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0, /* QSPIUSEFPGA */
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0, /* SPIS1USEFPGA */
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0, /* RGMII0USEFPGA */
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0, /* UART1USEFPGA */
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0, /* CAN1USEFPGA */
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0, /* USB1USEFPGA */
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0, /* I2C3USEFPGA */
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0, /* I2C2USEFPGA */
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0, /* I2C1USEFPGA */
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0, /* SPIM1USEFPGA */
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0, /* USB0USEFPGA */
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0 /* SPIM0USEFPGA */
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};
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#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
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