upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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155 lines
4.9 KiB
155 lines
4.9 KiB
16 years ago
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/*
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* Faraday FTMAC100 Ethernet
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*
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* (C) Copyright 2009 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __FTMAC100_H
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#define __FTMAC100_H
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struct ftmac100 {
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unsigned int isr; /* 0x00 */
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unsigned int imr; /* 0x04 */
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unsigned int mac_madr; /* 0x08 */
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unsigned int mac_ladr; /* 0x0c */
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unsigned int maht0; /* 0x10 */
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unsigned int maht1; /* 0x14 */
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unsigned int txpd; /* 0x18 */
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unsigned int rxpd; /* 0x1c */
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unsigned int txr_badr; /* 0x20 */
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unsigned int rxr_badr; /* 0x24 */
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unsigned int itc; /* 0x28 */
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unsigned int aptc; /* 0x2c */
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unsigned int dblac; /* 0x30 */
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unsigned int pad1[3]; /* 0x34 - 0x3c */
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unsigned int pad2[16]; /* 0x40 - 0x7c */
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unsigned int pad3[2]; /* 0x80 - 0x84 */
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unsigned int maccr; /* 0x88 */
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unsigned int macsr; /* 0x8c */
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unsigned int phycr; /* 0x90 */
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unsigned int phywdata; /* 0x94 */
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unsigned int fcr; /* 0x98 */
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unsigned int bpr; /* 0x9c */
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unsigned int pad4[8]; /* 0xa0 - 0xbc */
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unsigned int pad5; /* 0xc0 */
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unsigned int ts; /* 0xc4 */
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unsigned int dmafifos; /* 0xc8 */
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unsigned int tm; /* 0xcc */
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unsigned int pad6; /* 0xd0 */
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unsigned int tx_mcol_scol; /* 0xd4 */
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unsigned int rpf_aep; /* 0xd8 */
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unsigned int xm_pg; /* 0xdc */
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unsigned int runt_tlcc; /* 0xe0 */
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unsigned int crcer_ftl; /* 0xe4 */
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unsigned int rlc_rcc; /* 0xe8 */
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unsigned int broc; /* 0xec */
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unsigned int mulca; /* 0xf0 */
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unsigned int rp; /* 0xf4 */
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unsigned int xp; /* 0xf8 */
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};
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/*
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* Interrupt status register & interrupt mask register
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*/
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#define FTMAC100_INT_RPKT_FINISH (1 << 0)
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#define FTMAC100_INT_NORXBUF (1 << 1)
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#define FTMAC100_INT_XPKT_FINISH (1 << 2)
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#define FTMAC100_INT_NOTXBUF (1 << 3)
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#define FTMAC100_INT_XPKT_OK (1 << 4)
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#define FTMAC100_INT_XPKT_LOST (1 << 5)
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#define FTMAC100_INT_RPKT_SAV (1 << 6)
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#define FTMAC100_INT_RPKT_LOST (1 << 7)
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#define FTMAC100_INT_AHB_ERR (1 << 8)
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#define FTMAC100_INT_PHYSTS_CHG (1 << 9)
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/*
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* Automatic polling timer control register
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*/
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#define FTMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0)
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#define FTMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
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#define FTMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8)
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#define FTMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
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/*
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* MAC control register
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*/
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#define FTMAC100_MACCR_XDMA_EN (1 << 0)
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#define FTMAC100_MACCR_RDMA_EN (1 << 1)
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#define FTMAC100_MACCR_SW_RST (1 << 2)
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#define FTMAC100_MACCR_LOOP_EN (1 << 3)
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#define FTMAC100_MACCR_CRC_DIS (1 << 4)
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#define FTMAC100_MACCR_XMT_EN (1 << 5)
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#define FTMAC100_MACCR_ENRX_IN_HALFTX (1 << 6)
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#define FTMAC100_MACCR_RCV_EN (1 << 8)
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#define FTMAC100_MACCR_HT_MULTI_EN (1 << 9)
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#define FTMAC100_MACCR_RX_RUNT (1 << 10)
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#define FTMAC100_MACCR_RX_FTL (1 << 11)
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#define FTMAC100_MACCR_RCV_ALL (1 << 12)
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#define FTMAC100_MACCR_CRC_APD (1 << 14)
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#define FTMAC100_MACCR_FULLDUP (1 << 15)
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#define FTMAC100_MACCR_RX_MULTIPKT (1 << 16)
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#define FTMAC100_MACCR_RX_BROADPKT (1 << 17)
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/*
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* Transmit descriptor, aligned to 16 bytes
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*/
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struct ftmac100_txdes {
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unsigned int txdes0;
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unsigned int txdes1;
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unsigned int txdes2; /* TXBUF_BADR */
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unsigned int txdes3; /* not used by HW */
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} __attribute__ ((aligned(16)));
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#define FTMAC100_TXDES0_TXPKT_LATECOL (1 << 0)
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#define FTMAC100_TXDES0_TXPKT_EXSCOL (1 << 1)
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#define FTMAC100_TXDES0_TXDMA_OWN (1 << 31)
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#define FTMAC100_TXDES1_TXBUF_SIZE(x) ((x) & 0x7ff)
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#define FTMAC100_TXDES1_LTS (1 << 27)
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#define FTMAC100_TXDES1_FTS (1 << 28)
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#define FTMAC100_TXDES1_TX2FIC (1 << 29)
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#define FTMAC100_TXDES1_TXIC (1 << 30)
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#define FTMAC100_TXDES1_EDOTR (1 << 31)
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/*
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* Receive descriptor, aligned to 16 bytes
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*/
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struct ftmac100_rxdes {
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unsigned int rxdes0;
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unsigned int rxdes1;
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unsigned int rxdes2; /* RXBUF_BADR */
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unsigned int rxdes3; /* not used by HW */
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} __attribute__ ((aligned(16)));
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#define FTMAC100_RXDES0_RFL(des) ((des) & 0x7ff)
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#define FTMAC100_RXDES0_MULTICAST (1 << 16)
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#define FTMAC100_RXDES0_BROADCAST (1 << 17)
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#define FTMAC100_RXDES0_RX_ERR (1 << 18)
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#define FTMAC100_RXDES0_CRC_ERR (1 << 19)
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#define FTMAC100_RXDES0_FTL (1 << 20)
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#define FTMAC100_RXDES0_RUNT (1 << 21)
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#define FTMAC100_RXDES0_RX_ODD_NB (1 << 22)
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#define FTMAC100_RXDES0_LRS (1 << 28)
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#define FTMAC100_RXDES0_FRS (1 << 29)
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#define FTMAC100_RXDES0_RXDMA_OWN (1 << 31)
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#define FTMAC100_RXDES1_RXBUF_SIZE(x) ((x) & 0x7ff)
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#define FTMAC100_RXDES1_EDORR (1 << 31)
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#endif /* __FTMAC100_H */
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